Magnetic device and magnetic random access memory

Patent metadata

Field	Value
Publication number	US-2020136018-A1
Application number	US-201916592007-A
Country	US
Kind code	A1
Filing date	Oct 3, 2019
Priority date	Oct 29, 2018
Publication date	Apr 30, 2020
Grant date	—

Abstract

A magnetic memory including a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

First claim

What is claimed is:

1 . A magnetic memory, comprising:
a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate; and a second SOT-STT hybrid magnetic device disposed over the substrate; and a SOT conductive layer connected to the first and second SOT-STT devices, wherein: each of the first and second SOT-STT hybrid magnetic devices comprises:
a first magnetic layer, as a magnetic free layer;
a spacer layer disposed under the first magnetic layer; and
a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer,
the SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

2 . The magnetic memory of claim 1 , wherein the SOT conductive layer includes one or more layers of W, Ta, Mo and IrMn.

3 . The magnetic memory of claim 1 , wherein the SOT conductive layer includes a bottom layer made of W, Ta or Mo, and a top layer made of IrMn.

4 . The magnetic memory of claim 1 , further comprising an upper electrode layer disposed in contact with the SOT conductive layer.

5 . The magnetic memory of claim 4 , wherein the upper electrode layer includes a narrow portion having a width narrower than a remaining portion or a thin portion having a thickness smaller than the remaining portion over each of the first and second SOT-STT hybrid magnetic devices, the remaining portion being disposed between the first SOT-STT hybrid magnetic devices and the second SOT-STT hybrid magnetic device.

6 . The magnetic memory of claim 1 , wherein each of the first and second SOT-STT hybrid magnetic devices further comprises an interfacial layer disposed over the first magnetic layer and in contact with the SOT conductive layer.

7 . The magnetic memory of claim 1 , wherein the first magnetic layer is Fe x Co y Bi 1-x-y , 0.50≤x≤0.70 and 0.10≤y≤0.30.

8 . The magnetic memory of claim 7 , wherein the second magnetic layer includes at least one of a layer of Co, Fe and B, and a layer of Fe and B.

9 . The magnetic memory of claim 8 , wherein:
each of the first and second SOT-STT hybrid magnetic devices further comprises a third magnetic layer, as a bias layer, under the second magnetic layer, and the third magnetic layer includes a layer of Co and Fe.

10 . The magnetic memory of claim 9 , wherein each of the first and second SOT-STT hybrid magnetic devices further comprises a bottom electrode layer disposed under the third magnetic layer.

11 . The magnetic memory of claim 10 , wherein:
each of the first and second SOT-STT hybrid magnetic devices further comprises a STT switching device, one terminal of the STT switching device is coupled to the bottom electrode and another terminal of the switching device is coupled to a source line, the magnetic memory further comprises an SOT switching device, and one terminal of the SOT switching device is coupled to the SOT conductive layer and another terminal of the SOT switching device is coupled to the source line.

12 . The magnetic memory of claim 11 , wherein the source line is coupled to a current source.

13 . The magnetic memory of claim 11 , wherein the STT switching device and the SOT switching device are located below the first and second SOT-STT hybrid magnetic devices.

14 . A magnetic memory, comprising:
first word lines; a second word line; a bit line; a source line; memory cells; and a conductive wire, wherein: each of the memory cells includes a magnetic-tunneling-junction (MTJ) film stack and a spin-torque-transfer (STT) switching device, one terminal of the STT switching device is coupled to one end of the MTJ film stack, another terminal of the STT switching device is coupled to the source line and a control terminal of the STT switching device is coupled to corresponding one of the first word lines, another end of the MTJ film stack is coupled to the conductive wire, the conductive wire is coupled to the bit line, the magnetic memory further comprises a SOT switching device, and one terminal of the SOT switching device is coupled to the conductive wire, another terminal of the SOT switching device is coupled to the source line and a control terminal of the SOT switching device is coupled to the second word line.

15 . The magnetic memory of claim 14 , wherein the source line is coupled to a current source.

16 . The magnetic memory of claim 14 , wherein a number of the memory cells coupled to the conductive wire is in a range from 2 to 32.

17 . The magnetic memory of claim 14 , wherein:
the MTJ film stack includes:
a first magnetic layer, as a magnetic free layer;
a spacer layer disposed under the first magnetic layer; and
a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer, and
the conductive wire is disposed over the first magnetic layer.

18 . The magnetic memory of claim 14 , further comprising driver circuitry configured to:
apply a SOT current to the conductive wire by turning on the SOT switching device; and thereafter, apply a STT current to one of the memory cells by turning on the STT switching device coupled to the one of the memory cells, thereby writing data to the one of the memory cells.

19 . The magnetic memory of claim 18 , wherein the driver circuitry configured to:
turn off the STT switching device coupled to the one of the memory cells; and thereafter turn off the SOT switching device.

20 . A method of manufacturing a magnetic memory, comprising:
forming a plurality of magnetic-tunneling-junction (MTJ) film stacks, each including:
a first magnetic layer, as a magnetic free layer;
a spacer layer disposed under the first magnetic layer; and
a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer;
forming an interlayer dielectric layer to isolate the plurality of MTJ film stacks from each other; and forming a conductive wire over the plurality of MTJ film stacks to be coupled to the plurality of cell stacks, wherein the conductive wire includes a narrow portion having a width narrower than a remaining portion or a thin portion having a thickness smaller than the remaining portion over each of the plurality of MTJ film stacks, the remaining portion being disposed between adjacent MTJ film stacks.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Ying Ji-Feng
• Wang Jhong-Sheng
• Lin Tsann

Classifications

• H01F10/329

  Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect · CPC title

• G11C11/1659 Primary

  Cell access · CPC title

• H01F10/3254

  the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ] · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title