Three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-12048159-B2
Application number	US-202318129145-A
Country	US
Kind code	B2
Filing date	Mar 31, 2023
Priority date	Feb 27, 2020
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate including a first layer, a second layer, and a third layer that are sequentially stacked;
an electrode structure including electrodes that are stacked above the substrate;
a vertical channel structure that penetrates the electrode structure and is connected to the substrate; and
a separation structure that is at least partially on the substrate and that penetrates the electrode structure and divides the electrode structure,
wherein the separation structure includes:
a first vertical extended portion between a pair of lowermost electrodes of the electrodes that are adjacent to each other;
a second vertical extended portion under the first vertical extended portion; and
a neck portion interposed between the first vertical extended portion and the second vertical extended portion,

wherein the neck portion is located in the third layer,
wherein the second vertical extended portion extends horizontally in the second layer,
wherein a first width of the first vertical extended portion is smaller than a second width of the second vertical extended portion, and
wherein a bottom surface of the second vertical extended portion is higher than a bottom surface of the vertical channel structure.

2. The semiconductor memory device of claim 1 , further comprising a dummy structure that penetrates the electrode structure,
wherein the substrate has a cell array region and a connection region,
wherein a portion of the electrode structure and a portion of the separation structure extend over the cell array region and over the connection region,
wherein a portion of the vertical channel structure is provided on the cell array region, and
wherein a portion of the dummy structure is provided on the connection region.

3. The semiconductor memory device of claim 2 , wherein the vertical channel structure includes a first vertical semiconductor pattern and a first vertical insulating pattern that covers an outer surface of the first vertical semiconductor pattern, and
wherein the dummy structure includes a second vertical semiconductor pattern and a second vertical insulating pattern that covers an outer surface of the second vertical semiconductor pattern.

4. The semiconductor memory device of claim 1 , wherein a third width of the neck portion is smaller than the first width.

5. The semiconductor memory device of claim 1 , wherein the separation structure has an inflection point at which a width of the separation structure is changed abruptly between the neck portion and the second vertical extended portion.

6. The semiconductor memory device of claim 1 , wherein the vertical channel structure includes a first vertical semiconductor pattern and a first vertical insulating pattern that covers an outer surface of the first vertical semiconductor pattern, and wherein the second layer directly contacts the first vertical semiconductor pattern of the vertical channel structure.

7. The semiconductor memory device of claim 1 , further comprising:
a bit line electrically connected to the vertical channel structure;
an upper interconnection line electrically connected to the electrode structure; and
a peripheral circuit structure below the substrate,
wherein the bit line and the upper interconnection line are electrically connected to the peripheral circuit structure.

8. A semiconductor memory device, comprising:
a substrate including a first layer, a second layer, and a third layer that are sequentially stacked;
a first electrode structure and a second electrode structure adjacent to the first electrode structure, each of the first and second electrode structures including electrodes that are stacked above the substrate;
a first vertical channel structure that penetrates the first electrode structure and is connected to the substrate;
a second vertical channel structure that penetrates the second electrode structure and is connected to the substrate; and
a separation structure between the first and second electrode structures,
wherein the separation structure vertically extends from top surfaces of the first and second electrode structures toward the second layer,
wherein the separation structure includes:
a first vertical extended portion interposed between lower portions of the first and second electrode structures;
a second vertical extended portion under the first vertical extended portion; and
a neck portion interposed between the first vertical extended portion and the second vertical extended portion,

wherein the neck portion is located in the third layer,
wherein the second vertical extended portion extends horizontally in the second layer,
wherein a first width of the first vertical extended portion is smaller than a second width of the second vertical extended portion, and
wherein a bottom surface of the second vertical extended portion is higher than a bottom surface of each of the first and second vertical channel structures.

9. The semiconductor memory device of claim 8 , further comprising a dummy structure that penetrates the first electrode structure,
wherein the substrate has a cell array region and a connection region,
wherein portions of the first and second electrode structures and a portion of the separation structure extend above the cell array region and above the connection region,
wherein portions of the first and second vertical channel structures are provided on the cell array region, and
wherein a portion of the dummy structure is provided on the connection region.

10. The semiconductor memory device of claim 9 , wherein each of the first and second vertical channel structures includes a first vertical semiconductor pattern and a first vertical insulating pattern that covers an outer surface of the first vertical semiconductor pattern, and
wherein the dummy structure includes a second vertical semiconductor pattern and a second vertical insulating pattern that covers an outer surface of the second vertical semiconductor pattern.

11. The semiconductor memory device of claim 9 , wherein a third width of the neck portion is smaller than the first width.

12. The semiconductor memory device of claim 9 , wherein the separation structure has an inflection point at which a width of the separation structure is changed abruptly between the neck portion and the second vertical extended portion.

13. The semiconductor memory device of claim 8 , wherein each of the first and second vertical channel structures includes a first vertical semiconductor pattern and a first vertical insulating pattern that covers an outer surface of the first vertical semiconductor pattern, and
wherein the second layer directly contacts the first vertical semiconductor patterns of the first and second vertical channel structures.

14. The semiconductor memory device of claim 8 , further comprising:
a first bit line and a second bit line that are electrically connected to the first vertical channel structure and the second vertical channel structure, respectively;
a first upper interconnection line and a second upper interconnection line that are electrically connected to the first electrode structure and the second electrode structure, respectively; and
a peripheral circuit structure below the substrate,
wherein the first and second bit lines and the first and second upper interconnection lines are electrically connected to the peripheral circuit structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Seong-Hun
• Lee Byoungil
• Lee Joonhee

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title