Methods and apparatus for three-dimensional NAND non-volatile memory devices with side source line and mechanical support

US9780112B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9780112-B2
Application numberUS-201514922365-A
CountryUS
Kind codeB2
Filing dateOct 26, 2015
Priority dateOct 26, 2015
Publication dateOct 3, 2017
Grant dateOct 3, 2017

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Abstract

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A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate adjacent to the memory hole.

First claim

Opening claim text (preview).

The invention claimed is: 1. A three-dimensional stacked non-volatile memory structure comprising: a source line disposed above a substrate; a stack disposed above the substrate, the stack comprising alternating word line and dielectric layers; a plurality of NAND strings of memory cells formed in memory holes which extend through the source line and the alternating word line and dielectric layers, each memory cell comprising a control gate formed by one of the word line layers; and a mechanical support element disposed on the substrate adjacent the plurality of NAND strings, the mechanical support element extending through the source line. 2. The three-dimensional stacked non-volatile memory structure of claim 1 , wherein the mechanical support element comprises a plurality of mechanical support elements. 3. The three-dimensional stacked non-volatile memory structure of claim 2 , wherein the plurality of mechanical support elements is disposed along a peripheral region of the plurality of NAND strings. 4. The three-dimensional stacked non-volatile memory structure of claim 1 , wherein the mechanical support element comprises a first set of mechanical support elements disposed at a first region of the memory structure, a second set of mechanical support elements disposed at a second region of the memory structure, and a third mechanical support element disposed at a third region of the memory structure. 5. The three-dimensional stacked non-volatile memory structure of claim 4 , wherein the first region comprises a first peripheral region of the memory structure, the second region comprises a second peripheral region of the memory structure, and the third region comprises a central region of the memory structure. 6. The three-dimensional stacked non-volatile memory structure of claim 1 , wherein the mechanical support element extends to a height substantially equal to a height of a top surface of the source line. 7. The three-dimensional stacked non-volatile memory structure of claim 1 , wherein the mechanical support element has a height between about 500 angstroms and about 3500 angstroms. 8. The three-dimensional stacked non-volatile memory structure of claim 1 , wherein the mechanical support element comprises polysilicon. 9. The three-dimensional stacked non-volatile memory structure of claim 1 , wherein each of the NAND strings comprises a vertical channel comprising a peripheral exterior in contact with the source line. 10. The three-dimensional stacked non-volatile memory structure of claim 9 , wherein the vertical channel comprises polysilicon.

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What does patent US9780112B2 cover?
A method of fabricating a monolithic three dimensional memory structure is provided. The method includes forming a stack of alternating word line and dielectric layers above a substrate, forming a source line above the substrate, forming a memory hole extending through the alternating word line and dielectric layers and the source line, and forming a mechanical support element on the substrate …
Who is the assignee on this patent?
Sandisk Technologies Inc, Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification H01L27/11582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 03 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).