Three-dimensional semiconductor memory devices including first contact having a stepwise profile at interface between two portions

Patent metadata

Field	Value
Publication number	US-10354740-B2
Application number	US-201715842029-A
Country	US
Kind code	B2
Filing date	Dec 14, 2017
Priority date	Apr 25, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a substrate;
a stack structure on the substrate, the stack structure including electrodes that are vertically stacked on top of each other on a first region of the substrate;
a vertical structure penetrating the stack structure, the vertical structure including a first semiconductor pattern;
a data storage layer between the first semiconductor pattern and at least one of the electrodes;
a transistor on a second region of the substrate;
a first contact coupled to the transistor, the first contact including a first portion and a second portion on the first portion,
each of the first portion and the second portion having a diameter that increases with an increasing vertical distance from the substrate, and
a diameter of an upper part of the first portion being greater than a diameter of a lower part of the second portion; and
a dummy structure on a third region of the substrate, wherein
the stack structure extends onto the third region of the substrate and has a stepwise structure on the third region, and
the dummy structure penetrates the stack structure on the third region.

2. The 3D semiconductor memory device of claim 1 , further comprising:
a second contact coupled to the at least one of the electrodes of the stack structure,
wherein the second contact has a sidewall having a continuous profile.

3. The 3D semiconductor memory device of claim 1 , wherein the first contact has a sidewall having a stepwise profile at an interface between the first portion and the second portion.

4. The 3D semiconductor memory device of claim 1 , wherein
the transistor includes an active region and a gate electrode on the active region,
the active region of the transistor has a source/drain region, and
the first contact contacts a corresponding one of the source/drain region and the gate electrode.

5. The 3D semiconductor memory device of claim 1 , further comprising:
a buffer layer on the second region, and
an etch stop layer on the buffer layer, wherein
the buffer layer covers the transistor, and
the first contact penetrates the etch stop layer and the buffer layer.

6. The 3D semiconductor memory device of claim 5 , wherein
the transistor includes a gate electrode and a source/drain region, and
a top surface of the etch stop layer is at a higher level on the gate electrode of the transistor than on the source/drain region of the transistor.

7. The 3D semiconductor memory device of claim 5 , wherein the buffer layer has a planarized top surface.

8. The 3D semiconductor memory device of claim 1 , wherein the stack structure does not extend onto the second region.

9. The 3D semiconductor memory device of claim 1 , wherein the second region is one of a row decoder region, a page buffer region, a column decoder region, and a control circuit region.

10. A three-dimensional (3D) semiconductor memory device, comprising:
a substrate;
a stack structure on the substrate, the stack structure including electrodes that are vertically stacked on top of each other on a first region of the substrate;
a channel structure penetrating the stack structure;
a transistor on a second region of the substrate;
an interlayer dielectric layer on the stack structure and the transistor;
a first contact penetrating the interlayer dielectric layer, the first contact coupled to the transistor, a sidewall of the first contact having a stepwise profile;
a second contact penetrating the interlayer dielectric layer, the second contact coupled to at least one of the electrodes of the stack structure, and a sidewall of the second contact having a continuous profile; and
a buffer layer on the second region; and
an etch stop layer on the buffer layer, wherein
the buffer layer covers the transistor,
the buffer layer and the etch stop layer are between the interlayer dielectric layer and the transistor, and
the first contact penetrates the etch stop layer and the buffer layer.

11. The 3D semiconductor memory device of claim 10 , wherein
the first contact includes a first portion and a second portion on the first portion, and
a diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

12. The 3D semiconductor memory device of claim 10 , wherein the first contact and the second contact include a same conductive material.

13. The 3D semiconductor memory device of claim 10 , wherein top surfaces of the second contact, the first contact, and the interlayer dielectric layer are coplanar with each other.

14. A three-dimensional (3D) semiconductor memory device, comprising:
a substrate including a cell array region and a peripheral circuit region;
a stack structure on the cell array region, the stack structure including a memory cell array having a plurality of memory cells that are vertically stacked, the stack structure including word lines electrically connected to the plurality of memory cells;
a transistor on the peripheral circuit region;
a first contact electrically connected to the transistor;
a second contact electrically connected to the stack structure, a sidewall of the second contact having a different profile than a sidewall of the first contact; and
a first etch stop layer on the peripheral circuit region; and
a second etch stop layer on the first etch stop layer, wherein
the first etch stop layer covers the transistor,
the first etch stop layer and the second etch stop layers each independently include at least one of a silicon nitride layer, a silicon oxynitride layer, or a polysilicon layer, and
the first contact penetrates the first etch stop layer and the second etch stop layer.

15. The 3D semiconductor memory device of claim 14 , wherein the second contact is coupled to at least one of the word lines.

16. The 3D semiconductor memory device of claim 14 , wherein
the sidewall of the first contact has a stepwise profile, and
the sidewall of the second contact has a continuous profile.

17. The 3D semiconductor memory device of claim 14 , wherein a maximum diameter of the first contact is greater than a maximum diameter of the second contact.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kwang-Ho
• Yu Jihwan
• Cho Seunghyun

Classifications

• G11C11/412

  using field-effect transistors only · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• H01L27/11575

  Electricity · mapped topic