Three-dimensional memory device employing direct source contact and hole current detection and method of making the same

Patent metadata

Field	Value
Publication number	US-10199359-B1
Application number	US-201715669243-A
Country	US
Kind code	B1
Filing date	Aug 4, 2017
Priority date	Aug 4, 2017
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A three-dimensional memory device includes a p-doped source semiconductor layer located over a substrate, a p-doped strap semiconductor layer located over the p-doped source semiconductor layer, an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer, and memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer. Each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel. A top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region. A sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
a p-doped source semiconductor layer located over a substrate;
a p-doped strap semiconductor layer located over the p-doped source semiconductor layer;
an alternating stack of electrically conductive layers and insulating layers located over the p-doped strap semiconductor layer; and
memory stack structures that extend through the alternating stack and into an upper portion of the p-doped source semiconductor layer,

wherein:
each memory stack structure includes a p-doped vertical semiconductor channel and a memory film laterally surrounding the p-doped vertical semiconductor channel;
a top surface of each p-doped vertical semiconductor channel contacts a bottom surface of a respective n-doped region; and
a sidewall of a bottom portion of each p-doped vertical semiconductor channel contacts a respective sidewall of the p-doped strap semiconductor layer.

2. The three-dimensional memory device of claim 1 , wherein a bottom end of each memory film terminates above a horizontal plane including an interface between the p-doped source semiconductor layer and the p-doped strap semiconductor layer.

3. The three-dimensional memory device of claim 1 , further comprising memory material cap portions that underlie, and are vertically spaced from, each of the memory films, wherein the memory material cap portions are embedded within the p-doped source semiconductor layer.

4. The three-dimensional memory device of claim 3 , further comprising silicon oxide caps underlying the memory material caps and including a horizontal portion and a vertical peripheral portion that contacts a respective downward-protruding portion of the p-doped strap semiconductor layer.

5. The three-dimensional memory device of claim 1 , further comprising:
a p-doped etch stop semiconductor layer contacting a top surface of the p-doped strap semiconductor layer; and
silicon oxide rings contacting a respective one of the memory films and a respective sidewall of the p-doped etch stop semiconductor layer.

6. The three-dimensional memory device of claim 5 , wherein each of the silicon oxide rings contacts a respective upward-protruding portion of the p-doped strap semiconductor layer located above a horizontal plane including an interface between the p-doped strap semiconductor layer and the p-doped etch stop semiconductor layer.

7. The three-dimensional memory device of claim 6 , further comprising:
at least one dielectric layer and a metallic conductive layer located between the substrate and the p-doped source semiconductor layer;
a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack; and
a contact via structure extending through the retro-stepped dielectric material portion and electrically contacting the p-doped strap semiconductor layer.

8. The three-dimensional memory device of claim 1 , wherein each of the p-doped vertical semiconductor channels includes a laterally protruding ring that protrudes outward at a level of the p-doped strap semiconductor layer and contacts a respective laterally recessed sidewall of the p-doped strap semiconductor layer.

9. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of three-dimensional NAND strings over the silicon substrate, each of the three-dimensional NAND strings comprising a respective one of the memory stack structures;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings; and
the silicon substrate contains a peripheral device region comprising an integrated circuit comprising a driver circuit for the memory device located thereon.

10. The three-dimensional memory device of claim 1 , wherein each adjoining combination of the n-doped region and the p-doped vertical semiconductor channel constitutes a multi-gated p-n diode in which a read hole current is controlled by bias voltages applied to the electrically conductive layers during a reading step.

11. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device is configured to be read by providing a read hole current from the p-doped strap semiconductor layer to the p-doped vertical semiconductor channel; and
the three-dimensional memory device is configured to be erased by providing an erase hole current from the p-doped strap semiconductor layer to the p-doped vertical semiconductor channel.

Assignees

• Sandisk Technologies Llc

Inventors

• Sakakibara Kiyohiko
• Shimizu Satoshi
• Norizuki Naoto

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H05K7/023

  Stackable modules · CPC title

• H01L25/0652

  Electricity · mapped topic

• H01L25/0657 Primary

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic