Semiconductor package

Patent metadata

Field	Value
Publication number	US-12046562-B2
Application number	US-202318151517-A
Country	US
Kind code	B2
Filing date	Jan 9, 2023
Priority date	Jul 10, 2020
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A semiconductor package includes a first redistribution structure having a first surface in which a first pad and a second pad are embedded and including a first redistribution layer thereon, and a vertical connection structure including a land layer and a pillar layer. The land layer is embedded in the first surface of the first redistribution structure, and a width of an upper surface of the land layer is narrower than a width of a lower surface of the pillar layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first redistribution structure having an upper surface comprising a first pad and a second pad therein, and a lower surface opposite the upper surface and comprising a first redistribution layer electrically connected to the first pad and the second pad;
a vertical connection structure on the first pad of the first redistribution structure and comprising a land layer on the first pad, and a pillar layer on the land layer, the pillar layer having a lateral surface tapered in a first direction;
a semiconductor chip on the second pad of the first redistribution structure;
a first encapsulant on the upper surface of the first redistribution structure and covering the vertical connection structure, the first encapsulant having a lateral surface defining a cavity in which the semiconductor chip disposed and tapered in the first direction;
a second encapsulant on the first encapsulant and in the cavity; and
a first connection bump on the lower surface of the first redistribution structure and electrically connected to the first redistribution layer.

2. The semiconductor package as claimed in claim 1 , wherein the lateral surface of the vertical connection structure is tapered such that a width of the pillar layer increases toward the upper surface of the first redistribution structure.

3. The semiconductor package as claimed in claim 1 , wherein the lateral surface of the first encapsulant is tapered such that a width of the cavity increases toward the upper surface of the first redistribution structure.

4. The semiconductor package as claimed in claim 1 , wherein the first pad and the second pad are below the upper surface of the first redistribution structure.

5. The semiconductor package as claimed in claim 1 , wherein the land layer is below the upper surface of the first redistribution structure.

6. The semiconductor package as claimed in claim 1 , wherein a thickness of the first pad is greater than a thickness of the land layer of the vertical connection structure.

7. The semiconductor package as claimed in claim 1 , further comprising:
a second redistribution structure on the second encapsulant,
wherein the second redistribution structure comprises a second redistribution layer on the second encapsulant, and a second redistribution via extended from the second redistribution layer to the vertical connection structure.

8. The semiconductor package as claimed in claim 7 , wherein at least a portion of the second encapsulant covers an upper surface of the vertical connection structure, and
the second redistribution via penetrates through the at least a portion of the second encapsulant to electrically connect the second redistribution layer and the vertical connection structure.

9. The semiconductor package as claimed in claim 1 , further comprising:
a second connection bump between the semiconductor chip and the first redistribution structure, wherein the second connection bump electrically connects a connection electrode of the semiconductor chip and the second pad of the first redistribution structure.

10. A semiconductor package comprising:
a redistribution structure comprising an insulating layer, and first and second pads in the insulating layer;
a vertical connection structure on the redistribution structure, and electrically connected to the first pad;
a semiconductor chip on the redistribution structure and including a connection electrode electrically connected to the second pad; and
an encapsulant on the semiconductor chip and the vertical connection structure,
wherein the vertical connection structure comprises a land layer in the insulating layer and contacting the first pad, and a pillar layer on the land layer, and
wherein an upper surface of the first pad and an upper surface of the second pad are recessed, relative to an upper surface of the insulating layer.

11. The semiconductor package as claimed in claim 10 , wherein an upper surface of the land layer is substantially coplanar with the upper surface of the insulating layer.

12. The semiconductor package as claimed in claim 10 , wherein at least a portion of a lower surface of the pillar layer is in contact with the upper surface of the insulating layer.

13. The semiconductor package as claimed in claim 10 , wherein the land layer comprises a material having etch selectivity with respect to the first and second pads.

14. The semiconductor package as claimed in claim 10 , wherein a distance from the upper surface of the insulating layer to the upper surface of the first pad substantially equal to a distance from the upper surface of the insulating layer to the upper surface of the second pad.

15. A semiconductor package comprising:
a redistribution structure comprising an insulating layer, and first and second pads in the insulating layer;
a vertical connection structure on the redistribution structure, and electrically connected to the first pad;
a semiconductor chip on the redistribution structure and including a connection electrode electrically connected to the second pad; and
an encapsulant on the semiconductor chip and the vertical connection structure,
wherein the vertical connection structure comprises a land layer in the insulating layer and contacting the first pad, and a pillar layer on the land layer,
wherein the insulating layer has a first recess exposing the first pad, and a second recess exposing the second pad, and
wherein the land layer is disposed in the first recess.

16. The semiconductor package as claimed in claim 15 , wherein the first pad and the second pad are on a same level relative to a surface of the insulating layer.

17. The semiconductor package as claimed in claim 15 , wherein an upper surface of the first pad and an upper surface of the second pad have a step difference from an upper surface of the insulating layer.

18. The semiconductor package as claimed in claim 17 , wherein a thickness of the land layer is substantially equal to a height of the step difference.

19. The semiconductor package as claimed in claim 15 , wherein a width of the pillar layer increases in a direction toward the land layer.

20. The semiconductor package as claimed in claim 15 , wherein a width of the pillar layer is greater than each of a width of the land layer, a width of the first pad, and a width of the second pad.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Myungsam
• Ko Youngchan
• Kim Jeongseok
• Cho Bongju

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title