Wiring board and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-9420703-B2
Application number	US-201314237065-A
Country	US
Kind code	B2
Filing date	May 27, 2013
Priority date	Nov 7, 2012
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

To provide a wiring board in which wiring conductors are securely protected by a precise and rigid dam portion formed on an outermost layer of a laminate and that is excellent in connection reliability with a semiconductor chip. A laminate that configures this wiring board includes multiple connection terminal portions and wiring conductors as a conductor layer of the outermost layer. The wiring conductors are arranged at predetermined positions, passing through between multiple connection terminal portions for flip-chip mounting a semiconductor chip. A resin insulating layer of the outermost layer of the laminate has a dam portion and a reinforcement portion. The dam portion covers the wiring conductors. The reinforcement portion is formed, between the wiring conductor and the connection terminal portion that is adjacent to the wiring conductor, lower than a height of the dam portion. The reinforcement portion is concatenated with a side surface of the dam portion.

First claim

What is claimed is:

1. A wiring board comprising a laminate, in which one or more resin insulating layers and one or more conductor layers are stacked,
wherein the conductor layer of an outermost layer of the laminate comprises:
a plurality of connection terminal portions, which are disposed in a mounting area of a semiconductor chip and surfaces of which are exposed for flip-chip mounting the semiconductor chip; and
a wiring conductor that is arranged at a predetermined position between the plurality of connection terminal portions, and

wherein the resin insulating layer of the outermost layer of the laminate comprises:
a dam portion for covering the wiring conductor, the dam portion having a corner portion with a first curvature; and
a reinforcement portion, which is formed between the wiring conductor and the connection terminal portion adjacent to the wiring conductor and to be lower than a height of the dam portion, and which is concatenated with a side surface of the dam portion to form a concatenated region between the dam portion and the reinforcement portion, the concatenated region having a second curvature smaller than the first curvature.

2. The wiring board according to claim 1 ,
wherein the reinforcement portion fills between the wiring conductor and the connection terminal portion adjacent to the wiring conductor.

3. The wiring board according to claim 2 ,
wherein a height of the reinforcement portion is lower than a height of the plurality of connection terminal portions, and
wherein surfaces and upper portions of side surfaces of the plurality of connection terminal portions are exposed from the reinforcement portion.

4. The wiring board according to claim 1 ,
wherein the dam portion and the reinforcement portion are formed of a common solder-resist material and are formed in one piece.

5. A manufacturing method of the wiring board according to claim 1 , comprising:
a conductor layer formation step of forming the plurality of connection terminal portions and the wiring conductor in a mounting area of the semiconductor chip; and
a resin insulating layer formation step comprising:
forming the resin insulating layer of an outermost layer by arranging a resin insulating material having photosensitivity that becomes the resin insulating layer of the outermost layer on the plurality of connection terminal portions and the wiring conductor in a state where the resin insulating material covers the plurality of connection terminal portions and the wiring conductor and performing partial exposure and development on the resin insulating material; and
integrally forming the dam portion and the reinforcement portion.

Assignees

• Ngk Spark Plug Co

Inventors

• Hayashi Takahiro
• Nagai Makoto
• Ito Tatsuya
• Mori Seiji
• Wakazono Makoto
• Nishida Tomohiro

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/07227

  involving guiding structures, e.g. spacers or supporting members · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/01225

  in solid form, e.g. by using a powder or by stud bumping · CPC title