Chip package structure with bump and method for forming the same

Patent metadata

Field	Value
Publication number	US-9859245-B1
Application number	US-201615269514-A
Country	US
Kind code	B1
Filing date	Sep 19, 2016
Priority date	Sep 19, 2016
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. The chip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a first molding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.

First claim

What is claimed is:

1. A method for forming a chip package structure, comprising:
providing a first chip structure over a first carrier substrate;
forming a first molding layer surrounding the first chip structure;
disposing a second chip structure over the first chip structure;
forming a second molding layer surrounding the second chip structure;
forming a first solder bump over the second chip structure;
removing the first carrier substrate;
providing a redistribution substrate over a second carrier substrate;
bonding the second chip structure to the redistribution substrate through the first solder bump, wherein the second molding layer and the second chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between;
forming a third molding layer over the redistribution substrate and surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap; and
removing the second carrier substrate.

2. The method for forming a chip package structure as claimed in claim 1 , further comprising:
after the formation of the second molding layer and before the formation of the first solder bump, forming a conductive pillar over the second chip structure, wherein the first solder bump is formed over the conductive pillar.

3. The method for forming a chip package structure as claimed in claim 2 , wherein the conductive pillar is made of a first conductive material, the first solder bump is made of a second conductive material, a first melting point of the first conductive material is higher than a second melting point of the second conductive material, and the bonding of the second chip structure to the redistribution substrate through the first solder bump comprises:
disposing the first solder bump over the redistribution substrate; and
performing a reflow process on the first solder bump, wherein a temperature of the reflow process is between the first melting point and the second melting point.

4. The method for forming a chip package structure as claimed in claim 1 , further comprising:
after the formation of the first molding layer and before the disposing of the second chip structure, forming a conductive via structure over the first chip structure, wherein the second molding layer further surrounds the conductive via structure.

5. The method for forming a chip package structure as claimed in claim 4 , further comprising:
during the formation of the first solder bump forming a second solder bump over the conductive via structure.

6. The method for forming a chip package structure as claimed in claim 5 , further comprising:
after the formation of the second molding layer and before the formation of the second solder bump, forming a conductive pillar over the conductive via structure, therein the second solder bump is formed over the conductive pillar.

7. The method for forming a chip package structure as claimed in claim 1 , further comprising:
after the removal of the first carrier substrate and before the bonding of the second chip structure to the redistribution substrate, performing a sawing process over the first molding layer and the second molding layer.

8. The method for forming a chip package structure as claimed in claim 1 , wherein the formation of the second molding layer comprises:
forming the second molding layer over the first chip structure and the first molding layer.

9. The method for forming a chip package structure as claimed in claim 1 , further comprising:
after the formation of the first molding layer and before the disposal of the second chip structure over the first chip structure, forming an insulating layer over the first chip structure and the first molding layer, wherein the second chip structure and the second molding layer are over the insulating layer.

10. The method for forming a chip package structure as claimed in claim 9 , wherein the insulating layer separates the first molding layer and the first chip structure from the second chip structure and the second molding layer.

11. A method for forming a chip package structure, comprising:
forming a first molding layer surrounding a first chip structure;
disposing a second chip structure over the first drip structure;
forming a second molding layer surrounding the second chip structure;
forming a solder bump over the second chip structure;
bonding the second chip structure to a redistribution substrate through the solder bump, wherein the second molding layer and the second chip structure are both spared apart from the redistribution substrate by the solder bump, thereby defining a gap there-between; and
forming a third molding layer over the redistribution substrate and surrounding the first molding layer, the second molding layer, and the solder bump, and filled into the gap.

12. The method for forming a chip package structure as claimed in claim 11 , further comprising:
after the formation of the solder bump and before the bonding of the second chip structure to the redistribution substrate, performing a sawing process over the first molding layer and the second molding layer.

13. The method for forming a chip package structure as claimed in claim 12 , wherein after the sawing process, a first sidewall of the first molding layer and a second sidewall of the second molding layer are coplanar.

14. The method for forming a chip package structure as claimed in claim 12 , further comprising:
after the formation of the first molding layer and before the disposal of the second chip structure, forming an insulating layer over the first chip structure and the first molding layer, wherein the second chip structure and the second molding layer are over the insulating layer, and the sawing process is further performed over the insulating layer.

15. The method for forming a chip package structure as claimed in claim 14 , wherein after the sawing process, a first sidewall of the first molding layer, a second sidewall of the second molding layer, and a third sidewall of the insulating layer are coplanar.

16. The method for forming a chip package structure as claimed in claim 15 , wherein the third molding layer is in direct contact with the solder bump, the redistribution substrate, the first molding layer, the second molding layer, and the insulating layer.

17. A method for forming a chip package structure, comprising:
forming a first molding layer surrounding a first chip structure, wherein a first surface of the first molding layer and a second surface of the first chip structure are coplanar;
forming a conductive via structure over the first chip structure;
disposing a second chip structure over the first chip structure;
forming a second molding layer surrounding the second chip structure and the conductive via structure;
forming a solder bump over the second chip structure;
bonding the second chip structure to a redistribution substrate through the solder bump, wherein the second molding layer and the second chip structure are both spaced apart from the redistribution substrate by the solder bump, thereby defining a gap there-between; and
forming a third molding layer over the redistribution substrate and surrounding the first molding layer, the second molding layer, and the solder bump, and filled into the gap.

18. The method for forming a chip package structure as claimed in claim 17 , wherein a third surface of the conductive via structure and a fourth surface of the second molding layer are coplanar.

19.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Wei-Yu
• Huang Li-Hsien
• Su An-Jhih
• Chen Hsien-Wei

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title