Antenna in embedded wafer-level ball-grid array package

Patent metadata

Field	Value
Publication number	US-9806040-B2
Application number	US-201615219098-A
Country	US
Kind code	B2
Filing date	Jul 25, 2016
Priority date	Jul 29, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant over the semiconductor die to form a reconstituted wafer;
depositing a first conductive layer including an antenna onto a first surface of the reconstituted wafer after depositing the encapsulant; and
depositing a second conductive layer including a ground plane onto a second surface of the reconstituted wafer after depositing the encapsulant, wherein the antenna is located within a footprint of the ground plane.

2. The method of claim 1 , further including:
disposing a dummy die on the semiconductor die; and
depositing the encapsulant over the dummy die.

3. The method of claim 1 , further including disposing a conductive via adjacent to the semiconductor die prior to depositing the encapsulant.

4. The method of claim 3 , further including coupling the antenna to the semiconductor die through the conductive via.

5. The method of claim 3 , further including forming the antenna with the conductive via between the antenna and semiconductor die.

6. The method of claim 1 , further including:
forming an insulating layer over the first surface of the reconstituted wafer; and
forming a third conductive layer over the second surface of the reconstituted wafer with the insulating layer between the first conductive layer and third conductive layer.

7. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing a PCB unit adjacent to the semiconductor die;
depositing an encapsulant over the semiconductor die and PCB unit, wherein a first surface of the encapsulant, a first surface of the semiconductor die, and a first surface of the PCB unit are approximately coplanar;
forming an antenna over the PCB unit; and
forming a ground plane over the PCB unit, wherein at least one of the antenna or ground plane is formed over the first surface of the PCB unit, and at least one of the antenna or ground plane is formed over a second surface of the PCB unit opposite the first surface.

8. The method of claim 7 , further including:
providing a dummy die;
forming a conductive layer on the dummy die; and
disposing the dummy die over the semiconductor die prior to depositing the encapsulant.

9. The method of claim 8 , further including:
removing the dummy die by backgrinding the dummy die and encapsulant to expose the conductive layer;
forming a conductive bump on the conductive layer; and
disposing the semiconductor device over a substrate with the conductive layer coupled to the substrate by the conductive bump.

10. The method of claim 7 , further including coupling the antenna to the semiconductor die through the PCB unit.

11. The method of claim 7 , further including forming the ground plane and the antenna over the PCB unit prior to depositing the encapsulant.

12. The method of claim 7 , further including coupling the ground plane to the semiconductor die through the PCB unit.

13. The method of claim 7 , further including forming a conductive bump on the ground plane.

14. A semiconductor device, comprising:
a reconstituted wafer including,
a semiconductor die, and
an encapsulant deposited over the semiconductor die;

a first conductive layer including an antenna formed over a first surface of the reconstituted wafer; and
a second conductive layer including a ground plane formed over a second surface of the reconstituted wafer opposite the first surface.

15. The semiconductor device of claim 14 , further including a conductive via extending through the encapsulant adjacent the semiconductor die.

16. The semiconductor device of claim 15 , wherein the antenna is electrically coupled to the semiconductor die through the conductive via.

17. The semiconductor device of claim 14 , further including a PCB unit disposed between the ground plane and the antenna.

18. The semiconductor device of claim 17 , wherein the PCB unit includes a conductive via disposed between the antenna and semiconductor die.

19. The semiconductor device of claim 14 , wherein an active surface of the semiconductor die is coplanar with the first surface of the reconstituted wafer.

20. The semiconductor device of claim 14 , wherein an active surface of the semiconductor die is coplanar with the second surface of the reconstituted wafer.

21. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited over the semiconductor die to form a reconstituted wafer;
an antenna formed over the reconstituted wafer; and
a ground plane formed over the reconstituted wafer opposite the antenna.

22. The semiconductor device of claim 21 , further including a conductive bump formed over the ground plane.

23. The semiconductor device of claim 21 , further including a plurality of conductive vias formed through the encapsulant surrounding the semiconductor die.

24. The semiconductor device of claim 21 , further including a PCB unit disposed in the encapsulant.

25. The semiconductor device of claim 24 , wherein the antenna is coupled to the semiconductor die through the PCB unit.

Assignees

• Stats Chippac Pte Ltd

Inventors

• Liu Kai
• Lin Yaojian

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title