Semiconductor device using EMC wafer support system and fabricating method thereof

Patent metadata

Field	Value
Publication number	US-9627368-B2
Application number	US-201314083917-A
Country	US
Kind code	B2
Filing date	Nov 19, 2013
Priority date	Nov 20, 2012
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Provided are a semiconductor device using, for example, an epoxy molding compound (EMC) wafer support system and a fabricating method thereof, which can, for example, adjust a thickness of the overall package in a final stage of completing the device while shortening a fabricating process and considerably reducing the fabrication cost. An example semiconductor device may comprise a first semiconductor die that comprises a bond pad and a through silicon via (TSV) connected to the bond pad; an interposer comprising a redistribution layer connected to the bond pad or the TSV and formed on the first semiconductor die, a second semiconductor die connected to the redistribution layer of the interposer and positioned on the interposer; an encapsulation unit encapsulating the second semiconductor die, and a solder ball connected to the bond pad or the TSV of the first semiconductor die.

First claim

What is claimed is:

1. A method of fabricating a semiconductor device, the method comprising:
sequentially forming a seed layer and a copper layer on a top surface of a first semiconductor die that comprises a bond pad and a through silicon via (TSV);
forming a first encapsulation unit on the copper layer;
exposing the TSV by at least performing chemical mechanical polishing (CMP) on a bottom surface of the first semiconductor die;
forming an interposer comprising a redistribution layer connected to the TSV;
connecting a second semiconductor die to the redistribution layer of the interposer;
forming a second encapsulation unit encapsulating the second semiconductor die;
after forming the second encapsulation unit, exposing the copper layer by at least grinding the first encapsulation unit;
sequentially etching the copper layer and the seed layer; and
bonding a solder ball to the bond pad.

2. The method of claim 1 , wherein lateral surfaces of the first semiconductor die, the interposer, and the second encapsulation unit are coplanar.

3. The method of claim 1 , comprising forming a passivation layer on the bottom surface of the first semiconductor die laterally around an outside surface of the solder ball.

4. The method of claim 1 , wherein the redistribution layer of the interposer is at least laterally surrounded by a passivation layer.

5. The method of claim 1 , wherein said connecting a second semiconductor die to the redistribution layer of the interposer comprises positioning a conductive bump between the second semiconductor die and redistribution layer of the interposer.

6. The method of claim 1 , wherein a surface of the first encapsulation unit has the same area as a surface of the first semiconductor die.

7. The method of claim 1 , wherein the TSV has a length in a range of 20 to 70 μm.

8. The method of claim 1 , wherein the first semiconductor die has a thickness in a range of 400 to 500 μm.

9. A method of fabricating a semiconductor device, the method comprising:
forming a first encapsulation unit on a bottom surface of a first semiconductor die that comprises a bond pad and a through silicon via (TSV);
forming an interposer on a top surface of the first semiconductor die, the interposer comprising a redistribution layer connected to the TSV;
connecting a second semiconductor die to the redistribution layer of the interposer;
forming a second encapsulation unit encapsulating the second semiconductor die;
exposing the TSV by removing the first encapsulation unit using chemical mechanical polishing; and
bonding a solder ball to the TSV.

10. The method of claim 9 , wherein lateral surfaces of the first semiconductor die, the interposer, and the second encapsulation unit are coplanar.

11. The method of claim 9 , comprising forming a passivation layer on the bottom surface of the first semiconductor die laterally around an outside surface of the solder ball.

12. The method of claim 9 , wherein the redistribution layer of the interposer is at least laterally surrounded by a passivation layer.

13. The method of claim 9 , wherein said bonding a solder ball comprises forming an interconnection structure connected to the TSV and connecting the solder ball to the interconnection structure.

14. The method of claim 9 , wherein said exposing the TSV comprises removing material of the first semiconductor die.

15. The method of claim 9 , wherein the TSV has a length in a range of 20 to 70 μm.

16. The method of claim 9 , wherein the first semiconductor die has a thickness in a range of 400 to 500 μm.

17. A method of fabricating a semiconductor device comprising a lower first semiconductor die and an upper second semiconductor die electrically coupled to the lower first semiconductor die, the method comprising:
forming a first support structure below the lower first semiconductor die;
forming a seed layer and a copper layer between the lower first semiconductor die and the support structure;
after said forming the first support structure, electrically coupling the upper second semiconductor die to the lower first semiconductor die;
after said coupling the upper second semiconductor die to the lower first semiconductor die, forming an encapsulation layer above the upper second semiconductor die;
after said forming the encapsulation layer above the upper second semiconductor die, removing the entire support structure;
after removing the entire support structure, removing the seed layer and the copper layer.

18. The method of claim 17 , wherein said forming the support structure comprises forming a support encapsulation layer below the lower first semiconductor die while the lower first semiconductor die is in wafer form.

19. The method of claim 18 , wherein said electrically coupling the second semiconductor die to the first semiconductor die comprises forming an interposer that comprises a redistribution layer between the second semiconductor die and the first semiconductor die.

Assignees

• Amkor Technology Inc

Inventors

• Kim Jin Young
• Park Doo Hyun
• Yoon Ju Hoon
• Seo Seong Min
• Rinne Glenn
• Lee Choon Heung

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title