Microelectronic device with embedded die substrate on interposer

Patent metadata

Field	Value
Publication number	US-12046560-B2
Application number	US-202117555222-A
Country	US
Kind code	B2
Filing date	Dec 17, 2021
Priority date	Mar 29, 2017
Publication date	Jul 23, 2024
Grant date	Jul 23, 2024

Abstract

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

First claim

The invention claimed is:

1. A microelectronic device, comprising:
an embedded die in a dielectric body, the embedded die having a first side and a second side opposite the first side;
a first plurality of vertical contacts extending through the dielectric body, the first plurality of vertical contacts laterally adjacent to the first side of the embedded die;
a second plurality of vertical contacts extending through the dielectric body, the second plurality of vertical contacts laterally adjacent to the second side of the embedded die;
a first die electrically coupled to the embedded die, and the first die electrically coupled to and vertically overlapping the first plurality of vertical contacts;
a second die electrically coupled to the embedded die, the second die electrically coupled to and vertically overlapping the second plurality of vertical contacts, wherein there is no intervening die between the second die and the first die;
an insulative layer comprising interconnects, the insulative layer over the embedded die, over the first plurality of vertical contacts, and over the second plurality of vertical contacts;
first contact pads above a top surface of the insulative layer, the first contact pads coupled to the first die; and
second contact pads above the top surface of the insulative layer, the second contact pads coupled to the second die; and
a plurality of contacts beneath the dielectric body, wherein one or more of the plurality of contacts is coupled to a corresponding one or more of the first plurality of vertical contacts and the second plurality of vertical contacts without a routing layer there between.

2. A microelectronic device, comprising:
a first die in a dielectric body, the first die having a first side and a second side opposite the first side;
a first plurality of vertical contacts extending through the dielectric body, the first plurality of vertical contacts laterally adjacent to the first side of the first die;
a second plurality of vertical contacts extending through the dielectric body, the second plurality of vertical contacts laterally adjacent to the second side of the first die;
a second die electrically coupled to the first die, and the second die electrically coupled to and vertically overlapping the first plurality of vertical contacts;
a third die electrically coupled to the first die, the third die electrically coupled to and vertically overlapping the second plurality of vertical contacts, wherein there is no intervening die between the third die and the second die;
an insulative layer comprising interconnects, the insulative layer over the first die, over the first plurality of vertical contacts, and over the second plurality of vertical contacts;
first contact pads above a top surface of the insulative layer, the first contact pads coupled to the second die; and
second contact pads above the top surface of the insulative layer, the second contact pads coupled to the third die; and
a plurality of contacts beneath the dielectric body, wherein one or more of the plurality of contacts is coupled to a corresponding one or more of the first plurality of vertical contacts and the second plurality of vertical contacts without a routing layer there between.

3. The microelectronic device of claim 2 , wherein the first die is embedded in the dielectric body.

4. A microelectronic device, comprising:
an embedded die in a dielectric body, the embedded die having a top surface opposite a bottom surface, and the embedded die having a first side and a second side opposite the first side, the first side and the second side between the top surface and the bottom surface, wherein a portion of the dielectric body is on a portion of the top surface of the embedded die;
a first plurality of vertical contacts extending through the dielectric body, the first plurality of vertical contacts laterally adjacent to the first side of the embedded die;
a second plurality of vertical contacts extending through the dielectric body, the second plurality of vertical contacts laterally adjacent to the second side of the embedded die;
a first die electrically coupled to the embedded die, and the first die electrically coupled to and vertically overlapping the first plurality of vertical contacts;
a second die electrically coupled to the embedded die, the second die electrically coupled to and vertically overlapping the second plurality of vertical contacts;
an insulative layer comprising interconnects, the insulative layer over the embedded die, over the first plurality of vertical contacts, and over the second plurality of vertical contacts;
first contact pads above a top surface of the insulative layer, the first contact pads coupled to the first die; and
second contact pads above the top surface of the insulative layer, the second contact pads coupled to the second die; and
a plurality of contacts beneath the dielectric body, wherein one or more of the plurality of contacts is coupled to a corresponding one or more of the first plurality of vertical contacts and the second plurality of vertical contacts without a routing layer there between.

5. The microelectronic device of claim 4 , wherein the dielectric body is further on the bottom surface of the embedded die.

6. The microelectronic device of claim 4 , wherein the first plurality of vertical contacts and the second plurality of contacts extend below the bottom surface of the embedded die.

7. The microelectronic device of claim 4 , further comprising:
a dielectric layer on the dielectric body.

8. The microelectronic device of claim 7 , wherein the dielectric layer is between the first die and the dielectric body, and the dielectric layer is between the second die and the dielectric body.

9. The microelectronic device of claim 4 , wherein there is no intervening die between the second die and the first die.

10. The microelectronic device of claim 4 , wherein the first die extends laterally beyond the first side of the embedded die.

11. The microelectronic device of claim 10 , wherein the second die extends laterally beyond the second side of the embedded die.

12. A microelectronic device, comprising:
a first die having a top surface opposite a bottom surface, and the first die having a first side and a second side opposite the first side, the first side and the second side between the top surface and the bottom surface;
a dielectric body, wherein a first portion of the dielectric body is laterally adjacent to and in direct contact with the first side of the first die, a second portion of the dielectric body is laterally adjacent to and in direct contact with the second side of the first die, and a third portion of the dielectric body is on and in direct contact with a portion of the top surface of the first die;
a first plurality of vertical contacts laterally spaced apart from the first side of the first die, the first plurality of vertical contacts in and in direct contact with the first portion of the dielectric body, and the first plurality of vertical contacts extending through the first portion of the dielectric body;
a second plurality of vertical contacts laterally spaced apart from the second side of the first die, the second plurality of vertical contacts in and in direct contact with the second portion of the dielectric body, and the second plurality of vertical contacts extending through the second portion of the dielectric body;
a dielectric layer on the dielectric body;
a second die electrically coupled to the first die, and the second die electrically coupled to and vertically overlapping the first plurality of vertical contacts;
a third die electrically coupled

Assignees

• Intel Corp

Inventors

• May Robert Alan
• Salama Islam A
• Boyapati Sri Ranga Sai
• Li Sheng
• Darmawikarta Kristof
• Sankman Robert L
• Alur Amruthavalli Pallavi

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title