Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2018315764-A1
Application number	US-201715498743-A
Country	US
Kind code	A1
Filing date	Apr 27, 2017
Priority date	Apr 27, 2017
Publication date	Nov 1, 2018
Grant date	—

Abstract

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90° <θ1<115° measured from the upper surface of the erase gate.

First claim

1 . A method for manufacturing a semiconductor device including a non-volatile memory, the method comprising:
forming, over a substrate, a stacked structure including at least a first polysilicon layer and a second polysilicon layer; forming sidewall spacers on opposing sides of the stacked structure, wherein the sidewall spacers are simultaneously disposed over opposing sides of the first polysilicon layer and second polysilicon layer; forming a third polysilicon layer over the stacked structure, thereby covering the stacked structure; removing an upper portion of the third polysilicon layer, thereby forming a select gate and an erase gate, wherein an upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ 1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90° <θ1<115° measured from the upper surface of the erase gate.

2 . The method of claim 1 , wherein the one of the sidewall spacers is inclined toward a select gate side with respect to a normal line to a surface of the substrate, making an angle θ 2 between the one of the sidewall spacers and the normal line.

3 . The method of claim 2 , wherein θ° <θ 2 <10° measured from the normal line.

4 . The method of claim 2 , wherein the upper surface of the erase gate and a horizontal plane parallel to the surface of the substrate make an angle θ 3 at the contact point of the upper surface of the erase gate and the one of the sidewall spacers, where −15° <θ3<10° measured from the horizontal plane.

5 . The method of claim 1 , wherein the forming the stacked structure comprises:
forming a first dielectric layer over a substrate; forming a first polysilicon film for the first polysilicon layer over the first dielectric layer; forming a second dielectric film over the first polysilicon film; forming a second polysilicon film for the second polysilicon layer over the second dielectric film; patterning the second polysilicon film and the second dielectric film, thereby forming the second polysilicon layer and a second dielectric layer; after the second polysilicon layer and the second dielectric layer are formed, patterning the first polysilicon film, thereby forming the first polysilicon layer.

6 . The method of claim 5 , wherein:
the sidewall spacers include first sidewall spacers and second sidewall spacers, and the forming the stacked structure further comprises: after the second polysilicon film and the second dielectric film are patterned and before the first polysilicon film is patterned, forming the first sidewall spacers on opposing sides of the second polysilicon layer and the second dielectric layer, and after the first polysilicon film is patterned, forming the second sidewall spacers over opposing sides of the first polysilicon layer and the second polysilicon layer.

7 . (canceled)

8 . The method of claim 6 , wherein the first sidewall spacers have a three layer structure including at least one silicon nitride layer and at least one silicon oxide layer.

9 . A method for manufacturing a semiconductor device including a non-volatile memory, the method comprising:
forming, over a substrate, a stacked structure including at least a first polysilicon layer and a second polysilicon layer; forming sidewall spacers on opposing sides of the stacked structure; forming a third polysilicon layer over the stacked structure, thereby covering the stacked structure; removing an upper portion of the third polysilicon layer, thereby forming a select gate and an erase gate, wherein an upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle θ 1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90° <θ1<115° measured from the upper surface of the erase gate, wherein: the stacked structure further includes a cap insulating layer, and the removing an upper portion of the third polysilicon layer comprises: forming a planarization layer over the third polysilicon layer; performing a first etch-back operation using a first plasma process to partially remove the planarization layer and the third polysilicon layer, thereby exposing the cap insulating layer; and performing a second etch-back operation using a second plasma process to further reduce a thickness of the third polysilicon layer, thereby forming the select gate and the erase gate.

10 . The method of claim 9 , wherein the planarization layer is made of an organic material.

11 . The method of claim 10 , wherein the organic material has an attenuation coefficient between 0.2 to 0.6 with respect to 248 nm or 193 nm light.

12 . The method of claim 1 , wherein:
the stacked structure further includes a cap insulating layer, and the removing an upper portion of the third polysilicon layer comprises: forming a fourth polysilicon layer over the third polysilicon layer; performing a first planarization operation to partially remove the third and fourth polysilicon layers, thereby exposing the cap insulating layer; and performing a second planarization operation to further reduce a thickness of the third and fourth polysilicon layers, thereby forming the select gate and the erase gate.

13 . The method of claim 12 , wherein the first planarization operation includes a chemical mechanical polishing operation.

14 . The method of claim 12 , wherein the second planarization operation includes an etch-back operation using a plasma process.

15 - 20 . (canceled)

21 . A method for manufacturing a semiconductor device including a non-volatile memory, the method comprising:
forming, over a substrate, a stacked structure including at least a first polysilicon layer and a second polysilicon layer; forming sidewall spacers on opposing sides of the stacked structure; forming a third polysilicon layer over the stacked structure, thereby covering the stacked structure; removing an upper portion of the third polysilicon layer, thereby forming a select gate and an erase gate, wherein one of the sidewall spacers is inclined toward a select gate side with respect to a normal line to a surface of the substrate, making an angle θ 2 between the one of the sidewall spacers and the normal line, wherein 0° <θ2<10° measured from the normal line.

22 . The method of claim 21 , wherein the forming the stacked structure comprises:
forming a first dielectric layer over a substrate; forming a first polysilicon film for the first polysilicon layer over the first dielectric layer; forming a second dielectric film over the first polysilicon film; forming a second polysilicon film for the second polysilicon layer over the second dielectric film; patterning the second polysilicon film and the second dielectric film, thereby forming the second polysilicon layer and a second dielectric layer; and after the second polysilicon layer and the second dielectric layer are formed, patterning the first polysilicon film, thereby forming the first polysilicon layer; after the second polysilicon film and the second dielectric film are patterned and before the first polysilicon film is patterned, forming first sidewall spacers on opposing sides of the second polysilicon layer and the second dielectric layer, wherein the first sidewall spacers have a three layer structure including at least one silicon nitride layer and at least one silicon oxide layer.

23 . The method of claim 21 , wherein:
the stacked structure further includes a cap insulating layer, and the

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shihkuang
• Shih Hung-Ling
• Chiu Chieh-Fei
• Liu Po-Wei
• Huang Wen-Tuo
• Hsu Yu-Ling
• Tsair Yong-Shiuan

Classifications

• H01L21/3065

  Electricity · mapped topic

• H01L27/11521 Primary

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic

• H01L21/30625

  Electricity · mapped topic

• H10D30/711

  having floating bodies · CPC title