Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2019229123-A1
Application number	US-201916370736-A
Country	US
Kind code	A1
Filing date	Mar 29, 2019
Priority date	Jul 13, 2016
Publication date	Jul 25, 2019
Grant date	—

Abstract

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

First claim

What is claimed is:

1 . A semiconductor device including a non-volatile memory, wherein:
the non-volatile memory includes:
a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate;
first sidewalls made of a first dielectric material and disposed over opposing side faces of the stacked structure;
an erase gate line; and
a word line,
the word line includes a protrusion, and an upper portion of one of the first sidewalls located at a word line side is exposed from the word line.

2 . The semiconductor device of claim 1 , wherein a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate.

3 . The semiconductor device of claim 1 , wherein:
the stacked structure further includes second sidewalls made of a second dielectric material and disposed over opposing side faces of the stacked structure such that the second sidewalls are located between the first sidewalls and the stacked structure, and a height of one of the second sidewalls located the word line side is higher than a height of the one of the first sidewalls located at the word line side.

4 . The semiconductor device of claim 3 , wherein:
the second sidewalls are disposed on opposite side faces of the control gate and the third insulating layer, and the first sidewalls are disposed on opposite side faces of the floating gate.

5 . The semiconductor device of claim 1 , wherein:
the word line includes a first base portion and a second base portion, the protrusion is disposed between and protrude from the first base portion and the second base portion, and a height of the first base portion is different from a height of the second base portion.

6 . The semiconductor device of claim 5 , wherein:
the second base portion is disposed closer to the erase gate than the first base portion, and the height of the first base portion is smaller than the height of the second base portion.

7 . The semiconductor device of claim 5 , wherein a third sidewall made of an insulating material is disposed on a side face of the first base portion includes.

8 . The semiconductor device of claim 7 , wherein fourth sidewalls made of the insulating material are disposed on opposite side faces of the protrusion.

9 . The semiconductor device of claim 7 , wherein the third sidewalls and one of the fourth sidewalls of the protrusion located closer to the first base portion than the second base portion are discontinuous.

10 . The semiconductor device of claim 1 , wherein an upper surface of the protrusion inclines downward toward the stacked structure.

11 . The semiconductor device of claim 1 , wherein a height of the protrusion from the substrate is higher than a height of the control gate from the substrate.

12 . A semiconductor device including a non-volatile memory, wherein:
the non-volatile memory includes:
a first stacked structure and a second stacked structure, each comprising a first insulating layer, a floating gate, a second insulating layer and a control gate stacked in this order from a substrate;
first sidewalls disposed over opposing side faces of the first stacked structure;
second sidewalls disposed over opposing side faces of the second stacked structure;
an erase gate line disposed between the first stacked structure and the second stacked structure; and
a first word line and a second word line disposed such that the first stacked structure is disposed between the first word line and the erase gate line and the second stacked structure is disposed between the second word line and the erase gate line,
the first word line includes a first protrusion and the second word line includes a second protrusion, an upper portion of one of the first sidewalls located at a first word line side is exposed from the first word line, and an upper portion of one of the second sidewalls located at a second word line side is exposed from the second word line.

13 . The semiconductor device of claim 12 , wherein a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate.

14 . The semiconductor device of claim 12 , wherein the protrusion includes sidewall spacers made of an insulating material.

15 . The semiconductor device of claim 12 , wherein:
each of the first and second word lines includes a first base portion and a second base portion, the protrusion is disposed between and protrude from the first base portion and the second base portion, and a height of the first base portion is different from a height of the second base portion.

16 . The semiconductor device of claim 15 , wherein:
the second base portion is disposed closer to the erase gate than the first base portion, and the height of the first base portion is smaller than the height of the second base portion.

17 . The semiconductor device of claim 15 , wherein a third sidewall made of an insulating material is disposed on a side face of the first base portion.

18 . The semiconductor device of claim 17 , wherein:
fourth sidewalls made of the insulating material are disposed on opposite side faces of the protrusion, and the third sidewall and one of the fourth sidewalls located closer to the first base portion are discontinuous.

19 . The semiconductor device of claim 12 , wherein an upper surface of the protrusion inclines downward toward the stacked structure.

20 . A semiconductor device including a non-volatile memory and a logic circuit, wherein:
the non-volatile memory includes:
a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate;
first sidewalls made of a first dielectric material and disposed over opposing side faces of the stacked structure;
an erase gate line; and
a word line,
the logic circuit includes a field effect transistor comprising a gate electrode, the word line includes a protrusion, an upper portion of one of the first sidewalls located at a word line side is exposed from the word line, and the word line and the gate electrode are formed of polysilicon.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsao Tsun-Kai
• Shih Hung-Ling
• Liu Po-Wei
• Yang Shun-Shing
• Huang Wen-Tuo
• Tsair Yong-Shiuan
• Yang S K

Classifications

• H10P95/066

  the removal being a selective chemical etching step, e.g. selective dry etching through a mask · CPC title

• H01L21/31056

  Electricity · mapped topic

• H01L27/11529 Primary

  Electricity · mapped topic

• H01L21/28273

  Electricity · mapped topic

• H01L27/11521

  Electricity · mapped topic