Semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10325918-B2
Application number	US-201715428823-A
Country	US
Kind code	B2
Filing date	Feb 9, 2017
Priority date	Nov 29, 2016
Publication date	Jun 18, 2019
Grant date	Jun 18, 2019

Abstract

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device including a non-volatile memory, the method comprising:
forming a cell structure, the cell structure including:
a stacked structure including a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a first polysilicon layer as a floating gate disposed over the second dielectric layer, a third dielectric layer disposed over the first polysilicon layer, and a second polysilicon layer disposed over the third dielectric layer; and
third polysilicon layers disposed at both sides of the stacked structure;

removing the second polysilicon layer, thereby forming a control gate space; and
forming a conductive material in the control gate space,
wherein the forming the cell structure comprises:
forming a first dielectric film for the first dielectric layer over a substrate;
forming a second dielectric film for the second dielectric layer over the first dielectric film;
forming a first polysilicon film for the first polysilicon layer over the second dielectric film;
forming a third dielectric film for the third dielectric layer over the first polysilicon film;
forming a second polysilicon film for the second polysilicon layer over the third dielectric film;
patterning the second polysilicon film, thereby forming the second polysilicon layer;
after the second polysilicon layer is patterned, patterning the third dielectric film, the first polysilicon film and the second dielectric film, thereby forming the stacked structure;
forming third polysilicon films for the third polysilicon layers at both sides of the stacked structure; and
performing a planarization operation on the stacked structures and the third polysilicon films, thereby forming the third polysilicon layers.

2. The method of claim 1 , further comprising, after the second polysilicon layer is patterned and before the third dielectric film, the first polysilicon film and the second dielectric film are patterned, forming first sidewall spacers on opposing sides of the patterned second polysilicon layer.

3. The method of claim 2 , further comprising, after the first sidewall spacers are formed and before the third dielectric film, the first polysilicon film and the second dielectric film are patterned, forming second sidewall spacers over the first sidewall spacers.

4. The method of claim 3 , wherein the second sidewall spacers include an ONO film having a silicon nitride layer sandwiched by two silicon oxide layers.

5. The method of claim 3 , further comprising, after the third dielectric film, the first polysilicon film and the second dielectric film are patterned, forming third sidewall spacers on opposing sides of the stacked structure.

6. The method of claim 1 , wherein the second dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

7. The method of claim 6 , wherein the third dielectric layer is a silicon oxide layer, a silicon nitride layer or multilayers thereof.

8. The method of claim 6 , wherein the first dielectric layer is silicon oxide.

9. The method of claim 1 , wherein:
when the second polysilicon layer is removed, the third polysilicon layers are also at least partially removed, thereby forming a selection gate space and an erase gate space, and
the conductive material is also formed in the selection gate space and the erase gate space.

10. A method for manufacturing a semiconductor device including a non-volatile memory disposed in a memory cell area and a field effect transistor disposed in a logic circuit area, the method comprising:
forming a cell structure for the non-volatile memory in the memory cell area, the cell structure comprising:
a stacked structure including a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, a first polysilicon layer as a floating gate disposed over the second dielectric layer, a third dielectric layer disposed over the first polysilicon layer, and a second polysilicon layer disposed over the third dielectric layer; and
third polysilicon layers disposed at both sides of the stacked structure;

forming a first dummy gate structure for the field effect transistor in the logic circuit area, the first dummy gate structure comprising:
a first gate dielectric layer made of a same material as the second dielectric layer; and
a first dummy logic gate made of polysilicon and disposed over the first gate dielectric layer;

removing the second polysilicon layer in the memory cell area, thereby forming a control gate space, and removing the polysilicon of the first dummy logic gate, thereby forming a first logic gate space; and
forming a conductive material in the control gate space and the first logic gate space, respectively, wherein:
the second dielectric layer and the first gate dielectric layer include a dielectric material having a dielectric constant higher than silicon nitride and simultaneously formed by a same film formation operation, and
the cell structure and the first dummy logic gate structure are formed by:
forming a first dielectric film for the first dielectric layer over a substrate in the memory cell area;
after the first dielectric film is formed, forming a second dielectric film for the second dielectric layer and the first gate dielectric layer in the memory cell area and the logic circuit area;
forming a first polysilicon film for the first polysilicon layer and the first dummy logic gate over the second dielectric film in the memory cell area and the logic circuit area;
forming a third dielectric film for the third dielectric layer over the first polysilicon film in the memory cell area;
forming a second polysilicon film, for the second polysilicon layer and the first dummy logic gate, over the third dielectric film in the memory cell area and over the first polysilicon film in the logic circuit area;
patterning the second polysilicon film in the memory cell area, thereby forming dummy control gates and pattering the second polysilicon film and the first polysilicon film in the logic circuit area, thereby forming the first dummy logic gate;
after the second polysilicon film is patterned, patterning the third dielectric film and the first polysilicon film in the memory cell area, thereby forming the stacked structure;
forming third polysilicon films at the opposing sides of the stacked structure; and
performing a planarization operation on the stacked structures and the third polysilicon films in the memory cell area and the first dummy logic gate in the logic circuit area.

11. The method of claim 10 , further comprising, after the second polysilicon film is patterned and before the third dielectric film and the first polysilicon film are patterned, forming first sidewall spacers on opposing sides of the dummy control gates and on opposing sides of the first dummy logic gate.

12. The method of claim 11 , further comprising, after the first sidewall spacers are formed and before the third dielectric film and the first polysilicon film are patterned, forming second sidewall spacers over the first sidewall spacers.

13. The method of claim 12 , wherein the second sidewall spacers includes an ONO film having silicon nitride layer sandwiched by two silicon oxide layers.

14. The method of claim 10 , wherein:
when the second polysilicon layer is removed, the third polysilicon layers in the memory cell area are also at least partially removed, thereby forming a select gate space and an erase gate space, and
the conductive material is also formed in the select gate space and the erase gate sp

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Wei Cheng
• Teng Li-Feng

Classifications

• H01L27/11541

  Electricity · mapped topic

• H01L27/11531 Primary

  Electricity · mapped topic

• H01L27/11536

  Electricity · mapped topic

• H01L29/42344

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic