Ferroelectric or anti-ferroelectric trench capacitor with spacers for sidewall strain engineering

Patent metadata

Field	Value
Publication number	US-12040378-B2
Application number	US-202117336149-A
Country	US
Kind code	B2
Filing date	Jun 1, 2021
Priority date	Jun 13, 2019
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.

First claim

We claim:

1. A system comprising:
a processor circuitry to execute one or more instructions;
a memory coupled to the processor circuitry, wherein the memory is to store the one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory comprises:
a ferroelectric structure between two electrodes, wherein the ferroelectric structure has a polar orthorhombic phase, wherein the ferroelectric structure comprises a super lattice of a first material and a second material, and wherein:
the first material comprises one of: PbTiO 3 (PTO), SrZrO 3 , or FeO 3 ; and
the second material comprises one of: SrTiO 3 (STO), BaZrO 3 , or YTiO 3 ;

a material adjacent to one of the two electrodes, wherein the material provides tensile stress to the ferroelectric structure, and wherein the material comprises metal, semimetal, or oxide;
a first barrier structure adjacent to the one of the two electrodes; and
a second barrier structure adjacent to the other of the two electrodes, wherein the first and second barrier structures comprise Ta and N.

2. The system of claim 1 , wherein the two electrodes comprise metal comprising one or more of: Cu, Al, graphene, carbon nanotube, Au, Co, or Ti.

3. The system of claim 1 wherein the material comprises an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N.

4. The system of claim 1 , wherein the material has a thickness in a range of 5 Angstroms to 100 Angstroms.

5. The system of claim 1 , wherein a thickness of the ferroelectric structure is in a range of 2 nm to 30 nm.

6. A system comprising:
a processor circuitry to execute one or more instructions;
a memory coupled to the processor circuitry, wherein the memory is to store the one or more instructions; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory comprises:
an anti-ferroelectric material between a first electrode and a second electrode, wherein the anti-ferroelectric material forms a first surface at a first side of the anti-ferroelectric material, and a second surface at a second side of the anti-ferroelectric material, wherein the second side is opposite the first side, wherein the first electrode adjoins the anti-ferroelectric material at the first surface, wherein the second electrode adjoins the anti-ferroelectric material at the second surface, and wherein the anti-ferroelectric material has a tetragonal phase;
a material adjacent to the first electrode, wherein the material extends along opposite sidewalls of the first electrode, wherein the material provides tensile stress to the anti-ferroelectric material, and wherein the material comprises metal, semimetal, or oxide;
a first barrier structure adjacent to the first electrode; and
a second barrier structure adjacent to the second electrode, wherein the first and second barrier structures comprise Ta and N.

7. The system of claim 6 , wherein the first electrode and the second electrode comprise metal comprising one or more of: Cu, Al, graphene, carbon nanotube, Au, Co, or Ti.

8. The system of claim 6 wherein the material comprises an oxide of one or more of: Al, Ti, Hf, Si, Ir, or N.

9. The system of claim 6 , wherein the material has a thickness in a range of 5 Angstroms to 100 Angstroms.

Assignees

• Intel Corp

Inventors

• Haratipour Nazila
• Chang Sou-Chi
• Lin Chia-Ching
• Kavalieros Jack
• Avci Uygar
• Young Ian

Classifications

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D62/8161

  potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices (lateral superlattices, lateral surface superlattices H10D62/8181) · CPC title

• H10D62/862

  being Group II-VI materials comprising three or more elements, e.g. CdZnTe · CPC title

• H10D1/665

  Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title