Capacitors with ferroelectric/antiferroelectric and dielectric materials

Patent metadata

Field	Value
Publication number	US-2020286984-A1
Application number	US-201916296035-A
Country	US
Kind code	A1
Filing date	Mar 7, 2019
Priority date	Mar 7, 2019
Publication date	Sep 10, 2020
Grant date	—

Abstract

Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.

First claim

1 . A capacitor, comprising:
a first electrode; a second electrode; and an inter-electrode stack between the first electrode and the second electrode, wherein the inter-electrode stack includes a first layer including a first material, the inter-electrode stack includes a second layer including a second material, the first material is a dielectric material, and the second material is a ferroelectric material or an antiferroelectric material.

2 . The capacitor of claim 1 , wherein the second material includes silicon, lanthanum, nitrogen, aluminum, zirconium, or germanium.

3 . The capacitor of claim 1 , wherein the second material includes hafnium and yttrium.

4 . The capacitor of claim 1 , wherein the second material is a ferroelectric material.

5 . The capacitor of claim 1 , wherein the second material is an antiferroelectric material.

6 . The capacitor of claim 1 , wherein the inter-electrode stack further includes a third layer, the second layer is between the first layer and the third layer, and the third layer includes a dielectric material.

7 . The capacitor of claim 6 , wherein the third layer includes the first material.

8 . The capacitor of claim 6 , wherein the inter-electrode stack further includes a fourth layer, the third layer is between the second layer and the fourth layer, and the fourth layer includes a ferroelectric material or an antiferroelectric material.

9 . The capacitor of claim 8 , wherein the fourth layer includes the second material.

10 . The capacitor of claim 1 , wherein the inter-electrode stack further includes a third layer, the first layer is between the second layer and the third layer, and the third layer includes a ferroelectric material or an antiferroelectric material.

11 . The capacitor of claim 10 , wherein the third layer includes the second material.

12 . An integrated circuit (IC) die, comprising:
a capacitor, including:
a first electrode,
a second electrode, and
an inter-electrode stack between the first electrode and the second electrode, wherein the inter-electrode stack includes a first layer including a first material, the inter-electrode stack includes a second layer including a second material, the first material is a dielectric material, and the second material is a ferroelectric material or an antiferroelectric material.

13 . The IC die of claim 12 , wherein the first electrode is planar, and the second electrode is planar.

14 . The IC die of claim 12 , wherein the first electrode includes a trench and the inter-electrode stack is at least partially in the trench.

15 . The IC die of claim 14 , wherein the second electrode includes a projection that extends at least partially into the trench.

16 . The IC die of claim 12 , wherein the first electrode includes a plurality of trenches and the inter-electrode stack is at least partially in the plurality of trenches.

17 . The IC die of claim 16 , wherein the second electrode includes a plurality of projections, wherein an individual projection extends at least partially into an associated individual trench.

18 . The IC die of claim 12 , further comprising:
a transistor coupled to the capacitor.

19 . A computing device, comprising:
an integrated circuit (IC) package including a memory device, wherein the memory device includes a plurality of memory cells, and an individual one of the memory cells includes:
a transistor, and
a capacitor including two electrodes, a layer of ferroelectric or antiferroelectric material between the electrodes, and a layer of dielectric material between the electrodes.

20 . The computing device of claim 19 , wherein the memory device is a dynamic random access memory device.

Assignees

• Intel Corp

Inventors

• Chang Sou-Chi
• Lin Chia-Ching
• Penumatcha Ashish Verma
• Avci Uygar E
• Young Ian A

Classifications

• H10D1/714

  having horizontal extensions · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/684 Primary

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title

• H01L27/11507

  Electricity · mapped topic