Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-10211313-B2
Application number	US-201715678125-A
Country	US
Kind code	B2
Filing date	Aug 16, 2017
Priority date	Jul 17, 2017
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.

First claim

What is claimed is:

1. A method for fabricating semiconductor device, comprising:
forming a gate structure on a substrate;
forming an interlayer dielectric (ILD) layer around the gate structure;
removing the gate structure to form a first recess;
forming ferroelectric (FE) layer in the first recess;
forming a compressive layer on the FE layer;
performing a thermal treatment process directly on the compressive layer;
removing the compressive layer;
forming a work function metal layer in the recess;
forming a low resistance metal layer on the work function metal layer;
performing a planarizing process to form a metal gate;
removing part of the metal gate to form a second recess; and
forming a polysilicon layer in the second recess and on the ILD layer.

2. The method of claim 1 , further comprising:
forming a fin-shaped structure on the substrate; and
forming the gate structure on the fin-shaped structure, wherein the fin-shaped structure comprises silicon germanium.

3. The method of claim 1 , further comprising:
removing part of the polysilicon layer to form a third recess; and
forming a hard mask on the polysilicon layer.

4. The method of claim 1 , wherein the polysilicon layer comprises a n-type polysilicon layer.

5. The method of claim 1 , wherein the polysilicon layer is U-shaped.

6. The method of claim 1 , further comprising:
forming a high-k dielectric layer in the first recess; and
forming a bottom barrier metal (BBM) layer on the high-k dielectric layer before forming the FE layer.

7. The method of claim 1 , wherein the FE layer comprises HfZrO 2 .

8. The method of claim 1 , wherein the compressive layer comprises a compressive TiN layer.

Assignees

• United Microelectronics Corp

Inventors

• Tsai Shih-Hung
• Hsieh Po-Kuang
• Tseng Yu-Ting
• Kuo Cheng-Ping
• Tseng Kuan-Hao

Classifications

• H10P14/69397

  the material containing two or more metal elements · CPC title

• H10P14/69395

  the material containing zirconium, e.g. ZrO2 · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10D64/01356

  the insulator being formed after the semiconductor body, the semiconductor being a Group IV material and not being silicon, e.g. Ge, SiGe or SiGeC (H10D64/01364, H10D64/01366 take precedence) · CPC title