Semiconductor device including capacitor and method of forming the same

Patent metadata

Field	Value
Publication number	US-10825889-B2
Application number	US-201816012997-A
Country	US
Kind code	B2
Filing date	Jun 20, 2018
Priority date	Jan 11, 2018
Publication date	Nov 3, 2020
Grant date	Nov 3, 2020

Abstract

A semiconductor device including a switching element on a substrate, a pad isolation layer on the switching element, a conductive pad passing through the pad isolation layer and connected to the switching element, an insulating pattern on the pad isolation layer and having a height greater than a horizontal width, a lower electrode on side surfaces of the insulating pattern on side surfaces of the insulating pattern and in contact with the conductive pad, a capacitor dielectric layer on the lower electrode and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer an upper electrode on the capacitor dielectric layer may be provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a switching element on a substrate;
a pad isolation layer on the switching element;
a conductive pad configured to pass through the pad isolation layer and in contact with the switching element;
an insulating pattern on the pad isolation layer and configured to have a height greater than a horizontal width;
a lower electrode on side surfaces of the insulating pattern and in contact with the conductive pad;
a capacitor dielectric layer on the lower electrode and including a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer; and
an upper electrode on the capacitor dielectric layer.

2. The semiconductor device of claim 1 , wherein the lower electrode includes a monocrystalline perovskite lower conductive layer and a polycrystalline perovskite lower conductive layer.

3. The semiconductor device of claim 2 , wherein the monocrystalline perovskite lower conductive layer is relatively close to the side surfaces of the insulating pattern, compared to the polycrystalline perovskite lower conductive layer.

4. The semiconductor device of claim 2 , wherein the lower electrode includes SrRuO 3 , BaSnO 3 , (La, Sr)CoO 3 , (La, Sr)CuO 3 , (La, Sr)MnO 3 , LaNiO 3 , SrSnO 3 , SrMoO 3 , or a combination thereof.

5. The semiconductor device of claim 1 , wherein the monocrystalline dielectric layer includes a monocrystalline perovskite dielectric layer,
the polycrystalline dielectric layer includes a polycrystalline perovskite dielectric layer, and
the monocrystalline perovskite dielectric layer is relatively close to the side surfaces of the insulating pattern compared to the polycrystalline perovskite dielectric layer.

6. The semiconductor device of claim 1 , wherein the capacitor dielectric layer includes SrTiO 3 , BaTiO 3 , (Ba, Sr)TiO 3 , CaTiO 3 , PbTiO 3 , KTaO 3 , NaNbO 3 , HfPbO 3 , KNbO 3 , or a combination thereof.

7. The semiconductor device of claim 1 , wherein the capacitor dielectric layer includes a superlattice structure including at least two materials selected from among SrTiO 3 , BaTiO 3 , (Ba, Sr)TiO 3 , CaTiO 3 , PbTiO 3 , KTaO 3 , NaNbO 3 , HfPbO 3 , and KNbO 3 and alternately stacked on each other.

8. The semiconductor device of claim 1 , wherein the upper electrode includes a monocrystalline perovskite upper conductive layer and a polycrystalline perovskite upper conductive layer.

9. The semiconductor device of claim 8 , wherein the monocrystalline perovskite upper conductive layer is formed relatively close to the monocrystalline dielectric layer compared to the polycrystalline perovskite upper conductive layer.

10. The semiconductor device of claim 8 , wherein the upper electrode includes SrRuO 3 , BaSnO 3 , (La, Sr)CoO 3 , (La, Sr)CuO 3 , (La, Sr)MnO 3 , LaNiO 3 , SrSnO 3 , SrMoO 3 , or a combination thereof.

11. The semiconductor device of claim 1 , further comprising:
a seed layer having a monocrystalline perovskite material, and interposed between the insulating pattern and the lower electrode.

12. The semiconductor device of claim 11 , wherein the seed layer includes SrTiO 3 , BaTiO 3 , (Ba, Sr)TiO 3 , CaTiO 3 , PbTiO 3 , KTaO 3 , NaNbO 3 , HfPbO 3 , KNbO 3 , SrRuO 3 , BaSnO 3 , (La, Sr)CoO 3 , (La, Sr)CuO 3 , (La, Sr)MnO 3 , LaNiO 3 , SrSnO 3 , SrMoO 3 , or a combination thereof.

13. A semiconductor device comprising:
a first conductive pad and a second conductive pad apart from the first conductive pad;
a pad isolation layer between the first conductive pad and the second conductive pad;
an insulating pattern on the pad isolation layer and configured to have a height greater than a horizontal width;
a first lower electrode on a first side surface of the insulating pattern and in contact with the first conductive pad;
a second lower electrode on a second side surface of the insulating pattern and in contact with the second conductive pad;
a capacitor dielectric layer configured to cover the first and second lower electrodes, the insulating pattern, and the pad isolation layer, and having a monocrystalline dielectric layer and a polycrystalline dielectric layer, the monocrystalline dielectric layer being relatively close to first and second side surfaces of the insulating pattern compared to the polycrystalline dielectric layer; and
an upper electrode on the capacitor dielectric layer.

14. The semiconductor device of claim 13 , wherein each of the first and second lower electrodes includes:
a monocrystalline perovskite lower conductive layer; and
a polycrystalline perovskite lower conductive layer.

15. The semiconductor device of claim 14 , wherein
each of the first and second lower electrodes has a lower region having a horizontal width greater than a height, and an upper region having a height greater than a horizontal width, and
the upper region includes the monocrystalline perovskite lower conductive layer.

16. The semiconductor device of claim 15 , wherein the lower region of each of the first and second lower electrodes is in contact with the first conductive pad or the second conductive pad, and includes a portion of the monocrystalline perovskite lower conductive layer and the polycrystalline perovskite lower conductive layer.

17. A semiconductor device comprising:
a conductive pad on a substrate;
a pad isolation layer on the substrate and configured to surround the conductive pad;
an insulating pattern on the pad isolation layer and configured to have a height greater than a horizontal width;
a lower electrode on a side surface of the insulating pattern and in contact with the conductive pad;
a seed layer between the insulating pattern and the lower electrode and having a monocrystalline material;
a capacitor dielectric layer on the lower electrode; and
an upper electrode on the capacitor dielectric layer.

18. The semiconductor device of claim 17 , wherein the lower electrode includes a monocrystalline perovskite lower conductive layer.

19. The semiconductor device of claim 1 , wherein the insulating pattern upwardly extends from the pad isolation layer.

20. The semiconductor device of claim 17 , wherein the capacitor dielectric layer includes a monocrystalline dielectric layer and a polycrystalline dielectric layer, and the monocrystalline dielectric layer is relatively close to side surfaces of the insulating pattern compared to the polycrystalline dielectric layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Sang Yeol
• Cho Kyu Ho
• Lim Han Jin
• Hwang Cheol Seong

Classifications

• H10W44/601 Primary

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10D1/684

  the dielectrics comprising multiple layers, e.g. comprising buffer layers, seed layers or gradient layers · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title