Three-dimensional memory device with discrete charge storage elements and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12029037-B2
Application number	US-202117507224-A
Country	US
Kind code	B2
Filing date	Oct 21, 2021
Priority date	Oct 21, 2021
Publication date	Jul 2, 2024
Grant date	Jul 2, 2024

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers; and
memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel, a tunneling dielectric layer vertically extending through the alternating stack, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of silicon nitride memory elements,
wherein each of the silicon oxide blocking dielectric structures comprises a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.

2. The three-dimensional memory device of claim 1 , wherein the silicon oxynitride surface region contacts the respective one of the silicon nitride memory elements.

3. The three-dimensional memory device of claim 1 , wherein:
each of the silicon oxide blocking dielectric structures comprises a top surface contacting a respective first one of the insulating layers and a bottom surface contacting a respective second one of the insulating layers;
the top surface of each of the silicon oxide blocking dielectric structures comprises a respective first annular top surface in which an outer periphery is laterally offset from an inner periphery by a same lateral offset distance; and
the bottom surface of each of the silicon oxide blocking dielectric structures comprises a respective second annular bottom surface.

4. The three-dimensional memory device of claim 1 , wherein each of the silicon nitride memory elements comprises a top surface contacting a respective first one of the insulating layers and a bottom surface contacting a respective second one of the insulating layers.

5. The three-dimensional memory device of claim 4 , wherein:
the top surface of each of the silicon nitride memory elements comprises a respective first annular top surface in which an outer periphery is laterally offset from an inner periphery by a same lateral offset distance; and
the bottom surface of each of the silicon nitride memory elements comprises a respective second annular bottom surface.

6. The three-dimensional memory device of claim 1 , wherein each contiguous pair of a silicon oxide blocking dielectric structure of the silicon oxide blocking dielectric structures and a silicon nitride memory element of the silicon nitride memory elements has a same height.

7. The three-dimensional memory device of claim 1 , wherein the tunneling dielectric layer is in contact with inner sidewalls of the vertical stack of discrete silicon nitride memory elements within a respective one of the memory stack structures, and is in contact with each of the insulating layers in the alternating stack.

8. The three-dimensional memory device of claim 1 , wherein the vertical stack of discrete silicon oxide blocking dielectric structures does not contact, and is laterally spaced by the vertical stack of discrete silicon nitride memory elements from, the tunneling dielectric layer within each of the memory stack structures.

9. The three-dimensional memory device of claim 1 , wherein an outer tubular sidewall of the tunneling dielectric layer within each of the memory stack structures contacts each of the insulating layers, and vertically extends straight from a topmost layer within the alternating stack to a bottommost layer within the alternating stack.

10. The three-dimensional memory device of claim 1 , wherein:
the tunneling dielectric layer within each of the memory stack structures is laterally spaced from the insulating layers by a respective vertical stack of discrete silicon oxide spacers; and
an outer tubular sidewall of the tunneling dielectric layer within each of the memory stack structures vertically extends straight from a topmost layer within the alternating stack to a bottommost layer within the alternating stack.

11. The three-dimensional memory device of claim 1 , wherein an outer sidewall of the tunneling dielectric layer within each of the memory stack structures contacts each of the insulating layers, and vertically extends with lateral undulations from a topmost layer within the alternating stack to a bottommost layer within the alternating stack such that interfaces between the tunneling dielectric layer and the vertical stack of discrete silicon nitride memory elements are radially offset from interfaces between the tunneling dielectric layer and the insulating layers.

12. The three-dimensional memory device of claim 1 , wherein:
each of the electrically conductive layers is spaced from a most proximal pair of insulating layers of the insulating layers and from the memory stack structures by a backside blocking dielectric layer; and
the backside blocking dielectric layer comprises an upper horizontally-extending portion, a lower horizontally-extending portion, and a tubular portion that connects the upper horizontally-extending portion and the lower horizontally-extending portion and laterally surrounding a respective one of the memory stack structures.

Assignees

• Sandisk Technologies Llc

Inventors

• Tsutsumi Masanori
• Mukae Yusuke
• Hinoue Tatsuya
• Kasai Yuki

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title