Memory Hole Last Boxim

Patent metadata

Field	Value
Publication number	US-2016343718-A1
Application number	US-201514928385-A
Country	US
Kind code	A1
Filing date	Oct 30, 2015
Priority date	May 20, 2015
Publication date	Nov 24, 2016
Grant date	—

Abstract

Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

First claim

What is claimed is:

1 . A method of fabricating non-volatile storage, the method comprising:
forming alternating layers of a first material and a second material above a substrate having a major surface; etching holes in the alternating layers of the first material and the second material, wherein the holes have sidewalls that extend vertically with respect to the major surface; forming a sacrificial material in the holes; removing the layers of the first material while leaving in place the layers of the second material and the sacrificial material in the holes, leaving recesses where the first material was removed; forming a conductive material in the recesses; removing the sacrificial material from the holes after forming the conductive material in the recesses; and forming charge storage regions and channels of memory cells in the holes after removing the sacrificial material, wherein the conductive material forms control gates of the memory cells.

2 . The method of claim 1 , further comprising:
etching openings in the alternating layers of the first material and the second material, wherein removing the layers of the first material comprises: introducing an etchant into the openings.

3 . The method of claim 1 , further comprising:
depositing an etch stop layer on the sidewalls of the holes prior to forming the sacrificial material in the holes, wherein the etch stop layer has etch selectivity with respect to the first material.

4 . The method of claim 1 , further comprising:
forming a blocking layer of dielectric material in the recesses prior to forming the conductive material in the recesses.

5 . The method of claim 1 , further comprising:
forming a blocking layer of dielectric material between the charge storage regions and the conductive material.

6 . The method of claim 1 , wherein forming the charge storage regions comprises forming a charge storage layer that extends vertically in the holes, further comprising forming a tunnel dielectric layer on the charge storage layer, wherein forming the channels of memory cells comprises forming a conductive channel material on the tunnel dielectric layer.

7 . The method of claim 6 , further comprising:
forming a layer of oxide that extends vertically in the holes prior to forming the charge storage layer.

8 . The method of claim 1 , wherein forming the sacrificial material in the holes comprises:
forming an air gap within the sacrificial material.

9 . The method of claim 1 , further comprising:
forming a region of silicon at bottoms of the holes prior to forming the sacrificial material at least over the sidewalls of the holes; forming a protective layer of a material other than silicon on the region of silicon at the bottoms of the holes prior to forming the sacrificial material at least over the sidewalls of the holes; and removing the protective layer from the region of silicon after removing the sacrificial material from the holes and prior to forming the memory cells in the holes.

10 . The method of claim 9 , wherein the protective layer of the material other than silicon is a first protective material, and further comprising:
forming a second protective material other than the first protective material on sidewalls of the holes after removing the sacrificial material from the holes and prior to removing the first protective material from the region of silicon at the bottoms of the holes.

11 . The method of claim 1 , wherein the first material has an etch selectivity with respect to the second material, wherein the second material is an insulator.

12 . The method of claim 1 , wherein the first material is silicon oxide and the second material is silicon nitride.

13 . The method of claim 1 , wherein the sacrificial material comprises either amorphous silicon or polysilicon.

14 . A method of fabricating non-volatile storage, the method comprising:
forming alternating layers of an insulator and a sacrificial material above a substrate having a major surface, wherein the insulator has a major surface that extends parallel to the major surface of the substrate, wherein the sacrificial material has a major surface that extends parallel to the major surface of the substrate; etching openings in the alternating layers of the insulator and the sacrificial material, wherein the openings have sidewalls that are defined by the layers of the insulator and the sacrificial material; depositing an etch stop layer on the sidewalls of the openings; forming sacrificial nitride on the etch stop layer in the openings, wherein the sacrificial nitride extends vertically with respect to the major surfaces of the insulator and the sacrificial material; removing the layers of the sacrificial material while leaving in place the layers of the insulator and the sacrificial nitride in the openings, leaving recesses where the layers of sacrificial material were removed; forming a conductive material in the recesses; removing the sacrificial nitride from the openings after forming the conductive material in the recesses; and forming a memory film in the openings after removing the sacrificial nitride from the openings.

15 . The method of claim 14 , wherein forming the memory film in the openings after removing the sacrificial nitride from the openings comprises:
forming an inner blocking dielectric layer; forming charge storage regions of memory cells of NAND strings; and forming NAND string channels.

16 . The method of claim 14 , wherein forming the memory film in the openings comprises:
forming a charge trapping layer that comprises a dielectric material and that extends vertically with respect to the substrate.

17 . The method of claim 14 , wherein forming the memory film in the openings comprises:
forming a plurality of spaced-apart conductive floating gate material layers in each of the openings.

18 . The method of claim 14 , wherein the insulator is silicon oxide and the sacrificial material is silicon nitride.

19 . The method of claim 18 , further comprising:
etching slits in the alternating layers of silicon oxide and silicon nitride, wherein removing the layers of the silicon nitride comprises: introducing an etchant into the slits.

20 . The method of claim 19 , further comprising:
forming interconnects in the slits after removing the layers of the silicon nitride, wherein the interconnects are in electrical contact with the substrate.

21 . A method of fabricating non-volatile storage, the method comprising:
forming alternating layers of silicon oxide and silicon nitride above a substrate having a major surface; etching memory holes in the alternating layers of the silicon oxide and the silicon nitride, wherein the memory holes have vertical sidewalls that are defined by the layers of silicon oxide and silicon nitride; depositing an etch stop layer on the vertical sidewalls of the memory holes; forming silicon nitride on the etch stop layer in the memory holes, wherein the silicon nitride has an air gap; etching away the layers of the silicon nitride while leaving in place the layers of the silicon oxide and the silicon nitride in the memory holes, leaving recesses where the layers of silicon nitride were removed; depositing tungsten in the recesses; removing the silicon nitride from the memory holes after depositing the tungsten in the recesses; and forming vertically oriented NAND strings of non-volatile storage elements in the memory holes after removi

Assignees

• Sandisk Technologies Inc

Inventors

• Lu Zhenyu
• Kinoshita Hiro
• Mao Daxin
• Alsmeier Johann
• Shi Wenguang
• Dong Yingda
• Chien Henry
• Yamaguchi Kensuke
• Hu Xiaolong

Classifications

• H01L23/53257

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L21/76805

  Electricity · mapped topic

• H01L2221/1063

  Electricity · mapped topic