Semiconductor package

Patent metadata

Field	Value
Publication number	US-12015014-B2
Application number	US-202217679861-A
Country	US
Kind code	B2
Filing date	Feb 24, 2022
Priority date	Dec 13, 2019
Publication date	Jun 18, 2024
Grant date	Jun 18, 2024

Abstract

A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a plurality of semiconductor chips comprising a first semiconductor chip having a first active surface on which first connection pads are disposed and a first inactive surface opposing the first active surface, and a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which second connection pads are disposed and a second inactive surface opposing the second active surface,
a first adhesive layer disposed below the second inactive surface of the second semiconductor chip;
first bumps disposed directly on the first connection pads;
second bumps disposed directly on the second connection pads;
at least one first dummy bump directly on the first active surface of the first semiconductor chip and spaced apart from the first bumps;
a first filling layer covering the first active surface of the first semiconductor chip, side surfaces of the first bumps, and side surfaces of the at least one first dummy bump; and
at least one second dummy bump directly on the second active surface of the second semiconductor chip and spaced apart from the second bumps,
wherein the first bump does not overlap the second semiconductor chip in a vertical direction perpendicular to an upper surface of the first semiconductor chip, and
wherein the first adhesive layer is in contact with the second semiconductor chip, the first filling layer, and the at least one first dummy bump.

2. The semiconductor package of claim 1 , wherein an upper surface of the at least one first dummy bump is substantially coplanar with upper surfaces of the first bumps.

3. The semiconductor package of claim 1 , wherein the at least one first dummy bump overlaps the second semiconductor chip in a vertical direction perpendicular to an upper surface of the first semiconductor chip.

4. The semiconductor package of claim 1 , wherein a width of the at least one first dummy bump is greater than a width of one of the first bumps.

5. The semiconductor package of claim 1 , wherein the at least one first dummy bump includes a plurality of first dummy bumps spaced apart from each other.

6. The semiconductor package of claim 1 , wherein the first adhesive layer is spaced apart from the first bump.

7. The semiconductor package of claim 1 , further comprising:
a second filling layer covering the second active surface of the semiconductor chip, side surfaces of the second bumps, and side surfaces of the at least one second dummy bump.

8. The semiconductor package of claim 1 , further comprising:
a first insulating layer covering side surfaces of the first bump and the at least on first dummy bump on the first active surface of the first semiconductor chip; and
a first filling layer covering side surfaces of the first insulating layer and side surfaces of the first semiconductor chip.

9. The semiconductor package of claim 1 , further comprising:
a connection member disposed between the first semiconductor chip and the second semiconductor chip, the connection member comprising redistribution layers electrically connected to the first bumps.

10. A semiconductor package, comprising:
a plurality of semiconductor chips comprising a first semiconductor chip having a first active surface on which first connection pads are disposed and a first inactive surface opposing the first active surface, and a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which second connection pads are disposed and a second inactive surface opposing the second active surface;
a support member having a side surface facing a side surface of the first semiconductor chip;
first bumps disposed directly on the first connection pads;
first posts disposed directly on the first bumps and electrically connected to the first connection pads;
first dummy posts disposed side by side with the first posts and overlapping the support member in a vertical direction perpendicular to an upper surface of the first semiconductor chip; and
a connection member on the plurality of semiconductor chips and comprising redistribution layers electrically connected to each of the first and second posts.

11. The semiconductor package of claim 10 , wherein upper surfaces of the first posts are substantially coplanar with upper surfaces of the first dummy posts.

12. The semiconductor package of claim 10 , further comprising:
a first filling layer covering the first active surface of the first semiconductor chip and side surfaces of the first bumps; and
a second filling layer covering the second active surface of the semiconductor chip, side surfaces of the first posts, and side surfaces of the first dummy posts.

13. The semiconductor package of claim 10 , further comprising:
second posts disposed on the first posts, one of the second posts having a width different from a width of one of the first posts.

14. The semiconductor package of claim 10 , further comprising:
second bumps disposed directly on the second connection pads;
second posts disposed directly on the second bumps and electrically connected to the second connection pads; and
second dummy posts disposed side by side with the second posts and not overlapping the semiconductor chip in the vertical direction.

15. The semiconductor package of claim 10 , wherein the support member includes a plurality of insulating layers, a plurality of wiring layers buried in the insulating layers, and a plurality of vias electrically connecting the plurality of wiring layers to one another.

16. A semiconductor package, comprising:
a plurality of semiconductor chips;
a plurality of filling layers surrounding side surfaces of the plurality of semiconductor chips, respectively;
a connection member disposed on the plurality of filling layers;
a plurality of posts disposed in the plurality of filling layers; and
a plurality of bumps electrically connected to the plurality of semiconductor chips, respectively,
wherein the plurality of semiconductor chips comprises a first semiconductor chip and a second semiconductor chip partially overlapping the first semiconductor chip,
wherein the plurality of filling layers comprises a first filling layer surrounding a side surface of the first semiconductor chip and a second filling layer surrounding a side surface of the second semiconductor chip,
wherein the plurality of bumps comprises a first bump electrically connected to a first connection pad of the first semiconductor chip, and a second bump electrically connected to a second connection pad of the second semiconductor chip, and
wherein the plurality of posts comprises a first post penetrating the second filling layer on the first filling layer and electrically connected to the first bump, and a plurality of dummy posts penetrating the second filling layer.

17. The semiconductor package of claim 16 ,
wherein the plurality of semiconductor chips further comprises a third semiconductor chip disposed on the second semiconductor chip, and a fourth semiconductor chip disposed on the third semiconductor chip,
wherein the plurality of filling layers further comprises a third filling layer surrounding a side surface of the third semiconductor chip, and a fourth filling layer surrounding a side surface of the fourth semiconductor chip,
wherein the plurality of bumps further comprises a third bump electrically connected to a third connection pad of the third semiconductor chip, and a fourth bump electrically connected to a fourth connection pad of the fourth semicon

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Doohwan
• Byun Jungsoo

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title

• H10W72/856

  Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title