Semiconductor Device and Method of Forming POP Semiconductor Device with RDL Over Top Package
US-2016276307-A1 · Sep 22, 2016 · US
Pop devices and methods of forming the same
US9793246B1 · US · B1
| Field | Value |
|---|---|
| Publication number | US-9793246-B1 |
| Application number | US-201615215590-A |
| Country | US |
| Kind code | B1 |
| Filing date | Jul 21, 2016 |
| Priority date | May 31, 2016 |
| Publication date | Oct 17, 2017 |
| Grant date | Oct 17, 2017 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.
First claim
Opening claim text (preview).
What is claimed is: 1. A PoP device, comprising: a first package structure, comprising: a first chip; and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip; and a second package structure, comprising: a plurality active bumps bonded to the plurality of active through integrated fan-out vias; and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias, wherein a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip. 2. The PoP device of claim 1 , wherein a distribution of the active through integrated fan-out vias and the dummy through integrated fan-out vias at the first side of the first chip is substantially symmetrical to a distribution of the active through integrated fan-out vias and dummy through integrated fan-out vias at the second side of the first chip. 3. The PoP device of claim 1 , wherein a height of the active through integrated fan-out vias is substantially the same as a height of the dummy through integrated fan-out vias. 4. The PoP device of claim 1 , wherein a height of the active through integrated fan-out vias is different from a height of the dummy through integrated fan-out vias. 5. The PoP device of claim 1 , wherein a width of the active through integrated fan-out vias is substantially the same as a width of the dummy through integrated fan-out vias. 6. The PoP device of claim 1 , wherein a width of the active through integrated fan-out vias is different from a width of the dummy through integrated fan-out vias. 7. The PoP device of claim 1 , wherein the active through integrated fan-out vias are at the first side and the second side of the first chip, and the dummy through integrated fan-out vias are at one of the first side and the second side of the first chip. 8. The PoP device of claim 1 , wherein a total number of the active through integrated fan-out vias at the first side of the first chip is at least two times a total number of the active through integrated fan-out vias at the second side of the first chip. 9. The PoP device of claim 1 , wherein the active through integrated fan-out vias are at one of the first side and the second side of the first chip, and the dummy through integrated fan-out vias are at the other of the first side and the second side of the first chip. 10. A PoP device, comprising: a first package structure, comprising: a first chip; a plurality of active through integrated fan-out vias; a plurality of active pads electrically connected to the active through integrated fan-out vias; and a plurality of dummy pads aside the active pads; and a second package structure, comprising: a plurality of active bumps bonded to the active pads; and a plurality of dummy bumps bonded to the dummy pads, wherein the dummy pads are at one of a first side and a second side of the first chip. 11. The PoP device of claim 10 , wherein a total number of the active pads and the dummy pads at a first side of the first chip is substantially the same as a total number of the active pads and the dummy pads at a second side of the first chip. 12. The PoP device of claim 10 , wherein a distribution of the active pads and the dummy pads at a first side of the first chip is substantially symmetrical to a distribution of the active pads and dummy pads at a second side of the first chip. 13. The PoP device of claim 10 , wherein the active pads are at the first side and the second side of the first chip. 14. The PoP device of claim 10 , wherein the active pads are at the other of the first side and the second side of the first chip. 15. A PoP device, comprising: a first package structure, comprising: a first chip; and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip, wherein a dimension of the active through integrated fan-out vias is different from a dimension of the dummy through integrated fan-out vias; and a second package structure, comprising: a plurality of active bumps bonded to the active through integrated fan-out vias; and a plurality of dummy bumps bonded to the dummy through integrated fan-out vias. 16. The PoP device of claim 15 , wherein the dimension comprises a height, a width or both. 17. The PoP device of claim 15 , wherein a width of the active through integrated fan-out vias is substantially the same as a width of the dummy through integrated fan-out vias, and a height of the active through integrated fan-out vias is greater than a height of the dummy through integrated fan-out vias. 18. The PoP device of claim 15 , wherein a width of the active through integrated fan-out vias is greater than a width of the dummy through integrated fan-out vias, and a height of the active through integrated fan-out vias is greater than a height of the dummy through integrated fan-out vias. 19. The PoP device of claim 15 , wherein a total number of the active through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the dummy through integrated fan-out vias at a second side of the first chip. 20. The PoP device of claim 15 , wherein a distribution of the active through integrated fan-out vias at a first side of the first chip is substantially symmetrical to a distribution of the dummy through integrated fan-out vias at a second side of the first chip.
Assignees
Inventors
Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between stacked chips · CPC title
the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title
being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title
Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title
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Frequently asked questions
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- What does patent US9793246B1 cover?
- PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded …
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W70/09. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 17 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).