Semiconductor package embedded with plurality of chips and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9711482-B2
Application number	US-201514951727-A
Country	US
Kind code	B2
Filing date	Nov 25, 2015
Priority date	Sep 2, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. The semiconductor package may also include a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips. The semiconductor package may also include via patterns formed in the first encapsulation member. The semiconductor package may also include second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips. Second bonding pads electrically connected to the via patterns are arranged over bottom surfaces of the second semiconductor chips. The semiconductor package may also include a second encapsulation member formed over the top surfaces of the first semiconductor chips and the first encapsulation member to surround at least side surfaces of the second semiconductor chips.

First claim

What is claimed is:

1. A semiconductor package comprising:
first semiconductor chips disposed in a rotationally symmetrical structure, the first semiconductor chips including a plurality of first bonding pads arranged over the bottom surfaces of the first semiconductor chips, wherein the first bonding pads are arranged such that two groups of the first bonding pads each haying two rows are arranged in a direction in which an edge of the first semiconductor chip extends and the two row groups are spaced apart at a certain distance from one another;
a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips;
a plurality of via patterns formed in the first encapsulation member;
second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips, the second semiconductor chips including a plurality of second bonding pads electrically connected to the via patterns and arranged over bottom surfaces of the second semiconductor chips, wherein the second bonding pads are arranged such that two groups of the second bonding pads each having two rows are arranged in the direction in which the edge extends and the two row groups are spaced apart at a certain distance from one another; and
a second encapsulation member formed over the top surfaces of the first semiconductor chips and the first encapsulation member to surround at least side surfaces of the second semiconductor chips.

2. The semiconductor package according to claim 1 , wherein four first semiconductor chips are disposed in the rotationally symmetrical structure when viewed from above.

3. The semiconductor package according to claim 1 , wherein the first and second semiconductor chips have a rectangular plate shape and are stacked such that long edges of the first semiconductor chips and the second semiconductor chips are spaced apart from each other by a distance to form the step shapes.

4. The semiconductor package according to claim 1 , further comprising:
an adhesive member interposed between the first semiconductor chips and the second semiconductor chips.

5. The semiconductor package according to claim 1 , further comprising:
a substrate disposed over bottom surfaces of the first semiconductor chips and the first encapsulation member, wherein a top surface of the substrate faces the first semiconductor chips and a bottom surface of the substrate faces away from the top surface, and a plurality of first bond fingers are arranged over the top surface of the substrate and are electrically connected to the first bonding pads of the first semiconductor chips, and a plurality of second bond fingers are electrically connected to lower ends of the via patterns and a plurality of ball lands arranged over the bottom surface of the substrate.

6. The semiconductor package according to claim 5 , further comprising:
first bumps interposed between the first bonding pads of the first semiconductor chips and the first bond fingers of the substrate; and
second bumps interposed between the lower ends of the via patterns and the second bond fingers of the substrate.

7. The semiconductor package according to claim 5 , further comprising:
external connection members attached to the ball lands of the substrate.

8. The semiconductor package according to claim 1 , further comprising:
third bumps interposed between the second bonding pads of the second semiconductor chips and the via patterns.

9. The semiconductor package according to claim 1 , further comprising:
a first insulation layer formed over the bottom surfaces of the first semiconductor chips and the first encapsulation member to expose the first bonding pads and the via patterns;
redistribution lines formed over the first insulation layer to be electrically connected to the first bonding pads and the via patterns; a second insulation layer formed over the redistribution lines and the first insulation layer to expose portions of the redistribution lines; and
external connection members respectively formed over the exposed portions of the redistribution lines.

10. The semiconductor package according to claim 1 , further comprising:
a heat sink formed over the second semiconductor chips and the second encapsulation member.

Assignees

• Sk Hynix Inc

Inventors

• Lee Sang Eun
• Ko Eun
• Park Yong Jae

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/856

  Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title