Thin fan-out multi-chip stacked package structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9716080-B1
Application number	US-201615361073-A
Country	US
Kind code	B1
Filing date	Nov 25, 2016
Priority date	Jun 2, 2016
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

A thin fan-out multi-chip stacked package structure including a plurality of stacked chips is provided. The electrodes of the stacked chips and the active surface of the top chip are exposed. A dummy spacer is disposed on the active surface. Each bonding wire has a bonding thread bonded to a chip electrode and an integrally-connected vertical wire segment. A flat encapsulant encapsulates the chip stacked structure and the bonding wires. Polished cross-sectional surfaces of the bonding wires and a surface of the dummy spacer are exposed by the flat surface of the encapsulant. A redistribution layer structure is formed on the flat surface. A passivation layer covers the flat surface and the surface of the dummy spacer but exposes the polished cross-sectional surfaces. Fan-out circuits are formed on the passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires.

First claim

What is claimed is:

1. A thin fan-out multi-chip stacked package structure, comprising:
a chip stack formed by stacking a plurality of chips, wherein each of the chips has an active surface and at least one electrode located on the active surface, at least one electrode of a first chip is not covered by a second chip, and an active surface of the second chip is not stacked or covered by other chips in the chip stack;
a dummy spacer disposed on the active surface of the second chip, wherein at least one electrode of the second chip is not covered by the dummy spacer;
a plurality of bonding wires, wherein each of the bonding wires has a bonding thread and a vertical wire segment, and the bonding threads of the bonding wires are bonded to the electrodes of the chips and are integrally connected to the corresponding vertical wire segment;
an encapsulant encapsulating the chip stack and the bonding wires, wherein the encapsulant has a flat surface, and a plurality of polished cross-sectional surfaces of the bonding wires and the dummy spacer are coplanarly exposed by the flat surface; and
a redistribution layer structure formed on the flat surface, wherein the redistribution layer structure comprises a plurality of fan-out circuits, a first passivation layer, and a second passivation layer, the first passivation layer covers the flat surface and the dummy spacer while exposing the polished cross-sectional surfaces, the fan-out circuits are formed on the first passivation layer and are connected to the polished cross-sectional surfaces of the bonding wires via openings of the first passivation layer, and the second passivation layer is formed on the first passivation layer and covers the fan-out circuits.

2. The thin fan-out multi-chip stacked package structure of claim 1 , further comprising a plurality of external terminals connected to the redistribution layer structure to electrically connect with the fan-out circuits.

3. The thin fan-out multi-chip stacked package structure of claim 2 , wherein a plurality of terminal bearings are disposed between the external terminals and the fan-out circuits.

4. The thin fan-out multi-chip stacked package structure of claim 1 , wherein the chips are stacked in the manner of a ladder, a cross, or a tower.

5. The thin fan-out multi-chip stacked package structure of claim 1 , wherein the chips are stacked in a ladder offset manner to expose the electrodes, and the electrodes comprise a plurality of bonding pads.

6. The thin fan-out multi-chip stacked package structure of claim 1 , wherein the dummy spacer is a dummy chip or a metal plate.

7. The thin fan-out multi-chip stacked package structure of claim 1 , wherein an area of the dummy spacer exposed by the flat surface is less than or equal to an area of the active surface of the second chip such that peripheral sides of the dummy spacer are encapsulated by the encapsulant.

8. The thin fan-out multi-chip stacked package structure of claim 1 , wherein a length of the bonding wire connected between the first chip and the redistribution layer structure is greater than a length of the bonding wire connected between the second chip and the redistribution layer structure.

9. The thin fan-out multi-chip stacked package structure of claim 1 , wherein the chip stack further comprises a plurality of chip attachment layer disposed between two adjacent chips.

10. The thin fan-out multi-chip stacked package structure of claim 1 , further comprising a cladding layer disposed on a surface of the encapsulant.

11. A manufacturing method of a thin fan-out multi-chip stacked package structure, comprising:
providing a chip stack on a temporary carrier plate, wherein the chip stack is formed by stacking a plurality of chips, each of the chips has an active surface and at least one electrode located on the active surface, at least one electrode of a first chip is not covered by a second chip, and an active surface of the second chip is not stacked or covered by other chips in the chip stack;
disposing a dummy spacer on the active surface of the second chip, wherein at least one electrode of the second chip is not covered by the dummy spacer;
forming a plurality of first bonding wires connected between the chip stack and the dummy spacer, wherein each of the first bonding wires has a bonding thread, a vertical wire segment, a winding wire segment, and a wire end, the bonding threads of the first bonding wires are bonded to the electrodes of the chips, the bonding threads of the first boding wires are integrally connected to the corresponding vertical wire segment and are integrally connected to the wire ends via the winding wire segments, and the wire ends are bonded to the dummy spacer;
forming an encapsulant on the temporary carrier plate, wherein the encapsulant encapsulates the chip stack, the dummy spacer, and the first bonding wires;
grinding the encapsulant such that the encapsulant has a flat surface located at a different level than the active surface of the second chip, and removing the winding wire segments and the wire ends of the first bonding wires to form a plurality of second bonding wires, a plurality of polished cross-sectional surfaces of the second bonding wires and the dummy spacer are coplanarly exposed by the flat surface;
forming a redistribution layer structure on the flat surface, wherein the redistribution layer structure comprises a plurality of fan-out circuits, a first passivation layer, and a second passivation layer, the first passivation layer covers the flat surface and the dummy spacer while exposing the polished cross-sectional surfaces, the fan-out circuits are formed on the first passivation layer and are connected to the polished cross-sectional surfaces of the second bonding wires via openings the first passivation layer, and the second passivation layer is formed on the first passivation layer and covers the fan-out circuits; and
removing the temporary carrier plate.

12. The method of claim 11 , further comprising bonding a plurality of external terminals on the redistribution layer structure to electrically connect with the fan-out circuits.

13. The method of claim 11 , wherein the chips are stacked in the manner of a ladder, a cross, or a tower.

14. The method of claim 11 , wherein the chips are stacked in a ladder offset manner to expose the electrodes, and the electrodes comprise a plurality of bonding pads.

15. The method of claim 11 , wherein the dummy spacer is a dummy chip or a metal plate.

16. The method of claim 11 , wherein an area of the dummy spacer exposed by the flat surface is less than or equal to an area of the active surface of the second chip such that peripheral sides of the dummy spacer are encapsulated by the encapsulant.

17. The method of claim 11 , wherein during the step of grinding the encapsulant, at least a portion of the dummy spacer is grinded and the active surface of the second chip not stacked or covered by other chips in the chip stack is not grinded.

18. The method of claim 11 , further comprising forming a release layer between the chip stack and the temporary carrier plate.

19. The method of claim 18 , wherein the step of removing the temporary carrier plate comprises:
irradiating the release layer with an UV light; and
peeling off the release layer from the temporary carrier plate.

20. The method of claim 11 , further comprising forming a cladding layer on a surface of the encapsulant, wherein the cladding layer is an organic insulating layer or a thermally-conductive layer.

Assignees

• Powertech Technology Inc

Inventors

• Chuang Yong-Cheng
• Chang Chia-Wei

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title