Semiconductor package and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9966360-B2
Application number	US-201615202541-A
Country	US
Kind code	B2
Filing date	Jul 5, 2016
Priority date	Jul 5, 2016
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a first redistribution layer, a first die over the first redistribution layer, a molding compound encapsulating at least one second die and at least one third die disposed on the first redistribution layer, and at least one fourth die and conductive elements connected to the first redistribution layer. Through vias of the first die are electrically connected to through interlayer vias penetrating through the molding compound and are electrically connected to the first redistribution layer. The semiconductor package may further include a second redistribution layer disposed on the molding compound and between the first die, the second die and the third die.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first redistribution layer;
a first die disposed over the first redistribution layer and having at least one through via therein, wherein the first die comprises at least one sensor;
at least one second die and at least one third die, disposed on the first redistribution layer and between the first redistribution layer and the first die;
a molding compound disposed on the first redistribution layer, between the first redistribution layer and the first die, and encapsulating the at least one second die and the at least one third die,
through interlayer vias (TIVs) arranged through the molding compound, aside the at least one second die and the at least one third die, and between the first redistribution layer and the first die, wherein the TIVs electrically connect the first redistribution layer and the at least one through via of the first die;
a dielectric material layer disposed on the molding compound and between the molding compound, the at least one second die, the at least one third die and the first die, wherein the dielectric material layer exposes the at least one through via and the through interlayer vias;
conductive elements electrically connected to the first redistribution layer; and
at least one fourth die electrically connected to the first redistribution layer and aside the conductive elements.

2. The semiconductor package as claimed in claim 1 , wherein the at least one through via of the first die is in direct contact with the through interlayer vias in the molding compound.

3. The semiconductor package as claimed in claim 2 , wherein the at least one sensor comprises at least one fingerprint sensor, at least one CMOS sensor or a combination thereof.

4. A semiconductor package comprising:
a first redistribution layer;
a first die disposed over the first redistribution layer and having at least one through via therein, wherein the first die comprises at least one sensor;
at least one second die and at least one third die, disposed on the first redistribution layer and between the first redistribution layer and the first die;
a molding compound disposed on the first redistribution layer, between the first redistribution layer and the first die, and encapsulating the at least one second die and the at least one third die,
through interlayer vias (TIVs) arranged through the molding compound, aside the at least one second die and the at least one third die, and between the first redistribution layer and the first die, wherein the TIVs electrically connect the first redistribution layer and the at least one through via of the first die;
a second redistribution layer disposed on the molding compound between the first die and the at least one second and the third dies, wherein the at least one through via and the through interlayer vias are connected to the second redistribution layer, and the first die is electrically connected to the second redistribution layer by the at least one through via;
conductive elements electrically connected to the first redistribution layer; and
at least one fourth die electrically connected to the first redistribution layer and aside the conductive elements.

5. The semiconductor package as claimed in claim 4 , wherein the at least one sensor comprises at least one fingerprint sensor, at least one CMOS sensor or a combination thereof.

6. The semiconductor package as claimed in claim 1 , wherein the fourth die comprises at least one passive component and connectors are located between the fourth die and the first redistribution layer for electrically connecting the fourth die and the first redistribution layer.

7. A semiconductor package comprising:
a first die, comprising at least one sensor and through vias therein;
a first redistribution layer, disposed under the first die;
at least one second die and at least one third die, disposed on the first redistribution layer and between the first redistribution layer and the first die;
through interlayer vias (TIVs) disposed on the first redistribution layer and between the first redistribution layer and the first die, and the TIVs being disposed aside the at least one second die and the at least one third die, wherein locations of the through vias are substantially aligned with locations of the through interlayer vias, the through vias of the first die are electrically connected with the through interlayer vias, and the through vias and the through interlayer vias are electrically connected to the first redistribution layer; and
a molding compound, disposed on the first redistribution layer and between the first redistribution layer and the first die, wherein the molding compound encapsulates the at least one second die, the at least one third die and the through interlayer vias.

8. The semiconductor package as claimed in claim 7 , wherein the at least one sensor of the first die includes a fingerprint sensor or an image sensor and one end of the through via is directly connected to the through interlayer via and the other end of the through via is electrically connected to the at least one sensor.

9. The semiconductor package as claimed in claim 8 , further comprising conductive elements connected to the first redistribution layer and a dielectric material layer disposed on the molding compound and between the molding compound, the at least one second die, the at least one third die and the first die but exposing the through vias and the through interlayer vias.

10. The semiconductor package as claimed in claim 8 , wherein active surfaces of the at least one second die and the at least one third die are connected to the first redistribution layer.

11. The semiconductor package as claimed in claim 7 , further comprising a second redistribution layer disposed on the molding compound and between the molding compound, the at least one second die, the at least one third die and the first die, wherein the through vias and the through interlayer vias are connected to the second redistribution layer, and the first die is electrically connected to the second redistribution layer by the through via.

12. The semiconductor package as claimed in claim 11 , wherein the at least one sensor of the first die includes a fingerprint sensor or an image sensor and one end of the through via is directly connected to the second redistribution layer and the other end of the through via is electrically connected to the at least one sensor and two opposite ends of the through interlayer vias are respectively connected to the first and second redistribution layers.

13. The semiconductor package as claimed in claim 11 , wherein active surfaces of the at least one second die and the at least one third die are connected to the second redistribution layer.

14. A manufacturing method for semiconductor packages, comprising:
disposing a wafer comprising first dies on a carrier and each first die comprising at least one sensor and through vias therein;
forming through interlayer vias over the first die and over the through vias, wherein locations of the through vias are substantially aligned with locations of the through interlayer vias and the through interlayer vias are electrically connected to the through vias;
disposing at least one second die and at least one third die over the first die and aside the through interlayer vias;
forming a molding compound over the first dies of the wafer, encapsulating the at least one second die, the at least one third die and the through interlayer vias;
forming a first redistribution layer on the molding compound, wherein the through interlayer vias are electricall

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yu Chun-Hui
• Yee Kuo-Chung

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/7418

  of passive members, e.g. a chip mounting substrate · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P72/74 Primary

  using temporarily an auxiliary support · CPC title