Wrap-around projection liner for AI device

Patent metadata

Field	Value
Publication number	US-12010930-B2
Application number	US-202117470003-A
Country	US
Kind code	B2
Filing date	Sep 9, 2021
Priority date	Sep 9, 2021
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A semiconductor structure includes a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact, a metal layer disposed over each of the plurality of conductive lines, a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines, and a projection liner encapsulating the PCM element. Spacers directly contact sidewalls of the projection liner and the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a phase change memory (PCM) element horizontally and electrically connecting a first contact and a second contact; and
a projection liner encapsulating the PCM element including a backside surface of the PCM element to position a portion of the projection liner directly between the PCM element and the second contact.

2. The semiconductor structure of claim 1 , wherein spacers are formed adjacent the projection liner.

3. The semiconductor structure of claim 1 , wherein spacers directly contact sidewalls of the projection liner.

4. The semiconductor structure of claim 1 , wherein the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

5. The semiconductor structure of claim 4 , wherein a hardmask layer is formed over the GST layer.

6. The semiconductor structure of claim 5 , wherein sidewalls of the hardmask layer directly contact portions of the projection liner.

7. The semiconductor structure of claim 1 , wherein conductive lines are formed between the PCM element and the first and second contacts.

8. A semiconductor structure comprising:
a plurality of conductive lines formed within a dielectric, wherein each of the plurality of conductive lines electrically communicates with a respective contact;
a metal layer disposed over each of the plurality of conductive lines;
a phase change memory (PCM) element disposed over the metal layer of each of the plurality of conductive lines; and
a projection liner encapsulating the PCM element including both an upper surface and a backside surface of the PCM element, wherein a portion of the projection liner is directly between the PCM element and the metal layer.

9. The semiconductor structure of claim 8 , wherein spacers are formed adjacent the projection liner.

10. The semiconductor structure of claim 8 , wherein spacers directly contact sidewalls of the projection liner.

11. The semiconductor structure of claim 8 , wherein the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

12. The semiconductor structure of claim 11 , wherein a hardmask layer is formed over the GST layer.

13. The semiconductor structure of claim 12 , wherein sidewalls of the hardmask layer directly contact portions of the projection liner.

14. A method comprising:
forming a phase change memory (PCM) element;
horizontally and electrically connecting the PCM element to a first contact and a second contact; and
encapsulating the PCM element with a projection liner including a backside surface of the PCM element to position a portion of the projection liner directly between the PCM element and the second contact.

15. The method of claim 14 , further comprising forming spacers adjacent the projection liner.

16. The method of claim 14 , wherein the PCM element includes a GeSbTe (germanium-antimony-tellurium or GST) layer.

17. The method of claim 16 , further comprising forming a hardmask layer over the GST layer.

18. The method of claim 17 , wherein sidewalls of the hardmask layer directly contact portions of the projection liner.

19. The method of claim 14 , wherein the PCM element defines a fin-type GST cell.

20. The method of claim 14 , wherein the PCM element is formed by physical vapor deposition (PVD).

Assignees

• IBM

Inventors

• Ok Injo
• Chen Hsueh-Chung
• Silvestre Mary Claire
• Mignot Yann

Classifications

• H10N70/823 Primary

  adapted for essentially horizontal current flow, e.g. bridge type devices · CPC title

• H10N70/026

  by physical vapor deposition, e.g. sputtering · CPC title

• H10N70/8828

  Tellurides, e.g. GeSbTe · CPC title

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title