Resistive memory device including a lateral air gap around a memory element and method of making thereof

Patent metadata

Field	Value
Publication number	US-10050194-B1
Application number	US-201715478637-A
Country	US
Kind code	B1
Filing date	Apr 4, 2017
Priority date	Apr 4, 2017
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

First electrically conductive lines can be formed over a substrate. A two-dimensional array of vertical stacks can be formed, each of which includes a first electrode, an in-process resistive memory material portion, and a second electrode over the first electrically conductive line. The sidewalls of the in-process resistive memory material portions are laterally recessed with respect to sidewalls of the first electrode and the second electrode to form resistive memory material portions having reduced lateral dimensions. A dielectric material layer is formed by an anisotropic deposition to form annular cavities that laterally surround a respective one of the resistive memory material portions. Second electrically conductive lines can be formed on the second electrodes.

First claim

What is claimed is:

1. A resistive memory device, comprising:
a first electrically conductive line laterally extending along a first direction;
a vertical stack including, from bottom to top, a first electrode, a resistive memory material portion, and a second electrode, and contacting a top surface of the first electrically conductive line;
a second electrically conductive line extending along a second direction and contacting a top surface of the vertical stack;
a dielectric material contacting sidewalls of the first electrode and the second electrode; and
cavity located at a same level as the resistive memory material portion, laterally surrounds the resistive memory material portion, and laterally separates the dielectric material from the resistive memory material portion; and
at least one liner structure laterally surrounding the resistive memory material portion and laterally surrounded by the annular cavity,
wherein:
the cavity comprises an annular cavity that is free of any condensed phase material;
the dielectric material comprises a dielectric material layer which contacts a top surface of the first electrically conductive line, and a bottom surface of the second electrically conductive line;
the first electrode contacts a top surface of the first electrically conductive line and a bottom surface of the resistive memory material portion;
the second electrode contacts a bottom surface of the second electrically conductive line and a top surface of the resistive memory material portion; and
the at least one liner structure comprises:
a dielectric liner structure that includes an upper dielectric annular plate overlying the annular cavity, a lower dielectric annular plate underlying the annular cavity, and a dielectric tubular portion adjoined to an inner periphery of the upper dielectric annular plate and to an inner periphery of the lower dielectric annular plate; or
a metal nitride liner structure that includes an upper metal nitride annular plate overlying the annular cavity, a lower metal nitride annular plate underlying the annular cavity, and a metal nitride tubular portion adjoined to an inner periphery of the upper metal nitride annular plate and to an inner periphery of the lower metal nitride annular plate.

2. The resistive memory device of claim 1 , wherein the annular cavity is located between the top surface of the first electrode and the bottom surface of the second electrode.

3. The resistive memory device of claim 1 , wherein a sidewall of the resistive memory material portion is laterally recessed inward with respect to sidewalls of the first electrode and the second electrode.

4. The resistive memory device of claim 1 , wherein:
sidewalls of the first electrode and the second electrode extend along a vertical direction that is perpendicular to the first direction and the second direction; and
the sidewalls of the first electrode and the second electrode are vertically coincident with each other.

5. The resistive memory device of claim 4 , wherein a sidewall of the resistive memory material portion is laterally offset from the sidewalls of the first electrode and the second electrode by a uniform lateral offset distance that is independent of an azimuthal angle around a vertical axis passing through a geometrical center of the resistive memory material portion.

6. The resistive memory device of claim 1 , wherein each of the first electrode, the second electrode, and the resistive memory material portion has a respective cylindrical shape.

7. The resistive memory device of claim 1 , wherein the at least one liner structure comprises the dielectric liner structure that includes:
the upper dielectric annular plate overlying the annular cavity;
the lower dielectric annular plate underlying the annular cavity; and
the dielectric tubular portion adjoined to the inner periphery of the upper dielectric annular plate and to the inner periphery of the lower dielectric annular plate.

8. The resistive memory device of claim 1 , wherein the at least one liner structure comprises the metal nitride liner structure that includes:
the upper metal nitride annular plate overlying the annular cavity;
the lower metal nitride annular plate underlying the annular cavity; and
the metal nitride tubular portion adjoined to the inner periphery of the upper metal nitride annular plate and to the inner periphery of the lower metal nitride annular plate.

9. The resistive memory device of claim 1 , wherein the resistive memory material portion comprises a material selected from:
a phase change material portion providing at least two different levels of resistivity that depend on crystallinity of the phase change material;
a non-filamentary metal oxide portion providing at least two different levels of resistivity depending on concentration of oxygen vacancies therein; and
a filamentary metal oxide portion providing at least two different levels of resistivity depending on concentration of conductive filaments therein.

Assignees

• Sandisk Technologies Llc

Inventors

• Nardi Federico
• Fu Chu-Chen

Classifications

• H01L27/2436

  Electricity · mapped topic

• H01L45/1233 Primary

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic