Method for gate stack formation and etching

Patent metadata

Field	Value
Publication number	US-12009430-B2
Application number	US-202016782680-A
Country	US
Kind code	B2
Filing date	Feb 5, 2020
Priority date	Feb 22, 2019
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.

First claim

What is claimed is:

1. A method of patterning a gate structure on a substrate, the method comprising:
providing a patterned mask layer on the substrate, the patterned mask layer corresponding to a gate pattern;
providing an upper gate layer underlying the patterned mask layer, the upper gate layer comprising silicon;
providing a bottom gate layer underlying the upper gate layer, the bottom gate layer comprising silicon germanium (Si 1-x Ge x ), wherein a ratio of silicon to germanium in the Si 1-x Ge x is 0.1<X<0.4;
plasma etching the upper gate layer and the bottom gate layer with a halogen-based plasma to form the gate pattern in the upper gate layer and the bottom gate layer and form the gate structure, wherein the halogen-based plasma etches the bottom gate layer faster than the upper gate layer to reduce formation of silicon germanium residues near a bottom of the gate structure; and
after plasma etching the upper gate layer and the bottom gate layer, oxidizing the upper gate layer and the bottom gate layer to: (a) oxidize sidewall surfaces of the gate structure to form a sidewall oxide on the sidewall surfaces of the gate structure, and (b) oxidize any silicon germanium residues formed during the plasma etching to form oxide compounds near the bottom of the gate structure, the oxide compounds comprising a silicon germanium oxide (Si 1-x Ge x O z ) complex;
wherein said oxidizing preferentially oxidizes the silicon germanium residues formed near the bottom of the gate structure as opposed to oxidizing the sidewall surfaces of the gate structure.

2. The method of claim 1 , wherein the gate structure is a fin field effect transistor (FinFET) gate.

3. The method of claim 1 , wherein the ratio of silicon to germanium in the silicon germanium (Si 1-x Ge x ) enables: (a) the halogen-based plasma to etch the bottom gate layer faster than the upper gate layer to reduce the formation of the silicon germanium residues near the bottom of the gate structure, and (b) said oxidizing to preferentially oxidize the silicon germanium residues formed near the bottom of the gate structure as opposed to oxidizing the sidewall surfaces of the gate structure.

4. The method of claim 3 , wherein the bottom gate layer is thinner compared to the upper gate layer after the plasma etching of the upper gate layer and the bottom gate layer.

5. The method of claim 1 , further comprising removing the oxide compounds formed near the bottom of the gate structure.

6. The method of claim 5 , wherein the oxide compounds are removed with a wet etch.

7. The method of claim 1 , further comprising utilizing directional bombardment of oxygen ions to preferentially oxidize the silicon germanium residues formed near the bottom of the gate structure as opposed to oxidizing the sidewall surfaces of the gate structure.

8. The method of claim 1 , further comprising preferentially removing the oxide compounds formed near the bottom of the gate structure as opposed to the sidewall oxide formed on the sidewall surfaces of the gate structure.

9. The method of claim 7 , wherein a sublimation process is used to preferentially remove the oxide compounds at a higher removal rate than the sidewall oxide is removed.

10. The method of claim 9 , wherein conditions used during the sublimation process sublimate the silicon germanium oxide (Si 1-x Ge x O z ) complex without sublimating the sidewall oxide.

Assignees

• Tokyo Electron Ltd

Inventors

• Voronin Sergey
• Catano Christopher
• Han Sang Cheol
• Sridhar Shyam
• Yoshida Yusuke
• Talone Christopher
• Ranjan Alok

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6319

  Formation by plasma treatments, e.g. plasma oxidation of the substrate · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title