Three-dimensional semiconductor memory device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-11930639-B2
Application number	US-202217706426-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Jun 25, 2019
Publication date	Mar 12, 2024
Grant date	Mar 12, 2024

Abstract

A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device, comprising:
horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction parallel to a top surface of a substrate;
memory structures provided on the horizontal patterns, respectively, each of the memory structures comprising memory cells, which are three-dimensionally arranged;
penetrating insulating patterns, each being provided between adjacent ones of the horizontal patterns and being spaced apart from each other in a second direction crossing the first direction, each penetrating insulating pattern abutting side surfaces of the adjacent horizontal patterns;
through plugs extending through a corresponding penetrating insulating pattern to electrically connect the memory structures to the peripheral circuit structure; and
first and second separation structures disposed between the horizontal patterns, spaced apart from each other in the first direction and extending between the penetrating insulating patterns in the second direction and connected to adjacent ones of the penetrating insulating patterns,
wherein the horizontal patterns are portions of a first material layer,
wherein each of the penetrating insulating patterns penetrates the first material layer and have opposite borders that extend between side surfaces of the horizontal patterns and that are defined, at least in part, by the first material layer, and
wherein the three-dimensional semiconductor memory device comprises a dummy horizontal pattern, which is disposed between the penetrating insulating patterns and between the first and second separation structures.

2. The device of claim 1 , wherein, when measured in the first direction, a width of each of the first and second separation structures is larger than widths of the through plugs.

3. The device of claim 1 , wherein each of the first and second separation structures comprises:
a dummy plug disposed between the horizontal patterns, the dummy plug comprising a horizontal portion extending in the second direction and a vertical portion extending from the horizontal portion in a third direction perpendicular to the first and second directions; and
a dummy spacer interposed between the dummy plug and the horizontal patterns.

4. The device of claim 3 , wherein the dummy spacer is formed of a material different from the dummy plug.

5. The device of claim 3 , wherein the dummy plug is electrically floating.

6. A three-dimensional semiconductor memory device, comprising:
a peripheral circuit structure on a substrate;
horizontal semiconductor patterns disposed on the peripheral circuit structure, the horizontal semiconductor patterns spaced apart from each other in a first direction parallel to a top surface of the substrate;
penetrating insulating patterns provided adjacent to corresponding ones of the horizontal semiconductor patterns, the penetrating insulating patterns spaced apart from each other in a second direction crossing the first direction between the horizontal semiconductor patterns, each of the penetrating insulating patterns connected to the horizontal semiconductor patterns in the first direction; and
separation structures vertically extending higher than top surfaces of the horizontal semiconductor patterns, the separation structures disposed between the penetrating insulating patterns and between the horizontal semiconductor patterns, each of the separation structures are spaced apart from each other in the first direction and connected to corresponding penetrating insulating patterns in the second direction,
wherein, when viewed in a plan view, each of the horizontal semiconductor patterns is isolated by corresponding ones of the penetrating insulating patterns and the separation structures such that the horizontal semiconductor patterns are separated from each other, and
wherein each penetrating insulating pattern is in contact with a side surface of at least one corresponding one of the horizontal semiconductor patterns.

7. The device of claim 6 , wherein each of the horizontal semiconductor patterns has a first width in a first horizontal direction extending between a pair of the penetrating insulating patterns on opposite sides of the horizontal semiconductor pattern and has a second width, which is larger than the first width, in the first horizontal direction extending between a pair of the separation structures on the opposite sides of the corresponding horizontal semiconductor pattern.

8. The device of claim 6 ,
wherein the device further comprises through plugs, which penetrate corresponding ones of the penetrating insulating patterns to connect to the peripheral circuit structure, and
wherein at least some of the separation structures comprise an insulator, which is in contact with a corresponding pair of adjacent ones of the penetrating insulating patterns and a corresponding horizontal semiconductor pattern.

9. The device of claim 6 , further comprising metal plate patterns in contact with bottom surfaces of corresponding ones of the horizontal semiconductor patterns,
wherein at least some of the penetrating insulating patterns are in contact with a side surface of a corresponding horizontal semiconductor pattern and a side surface of a corresponding metal plate pattern.

10. The device of claim 9 , wherein at least some of the separation structures comprises a dummy spacer, which is in contact with corresponding adjacent ones of the penetrating insulating patterns, a side surface of a corresponding horizontal semiconductor pattern, and a side surface of a corresponding metal plate pattern.

11. The device of claim 6 ,
wherein the horizontal semiconductor patterns each comprises first and second horizontal semiconductor sub-patterns, which are sequentially stacked on the peripheral circuit structure,
wherein each penetrating insulating pattern is in contact with side surfaces of corresponding first and second horizontal semiconductor sub-patterns, and
wherein the device further comprises through plugs, which penetrate corresponding ones of the penetrating insulating patterns to connect to the peripheral circuit structure.

12. The device of claim 11 , wherein each separation structure comprises vertical portions that extend in a direction perpendicular to a top surface of the horizontal semiconductor patterns, and a horizontal portion extending horizontally to connect the vertical portions of the corresponding separation structure.

13. The device of claim 6 , further comprising:
a stack of electrodes on each of the horizontal semiconductor patterns, each stack having a staircase structure in-on an edge region of the corresponding horizontal semiconductor pattern on which it is stacked; and
vertical structures penetrating the stacks,
wherein the penetrating insulating patterns and the separation structures are disposed between the staircase structures of corresponding adjacent ones of the stacks.

14. A three-dimensional semiconductor memory device, comprising:
a peripheral circuit structure comprising a substrate and peripheral logic circuits formed with the substrate;
horizontal patterns disposed on the peripheral circuit structure and spaced apart from each other in a first direction;
memory structures provided on the horizontal patterns, respectively, each of the memory structures comprising memory cells, which are three-dimensionally arranged;
a separation structure disposed between adjacent ones of the horizontal patterns;
first and second penetrating insulating patterns provided between and contacting side surfaces of adjacent ones

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Woosung
• Lee Dong-Sik
• Hwang Sung-Min
• Lim Joon-Sung

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D64/037

  comprising charge-trapping insulators · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title