Method and apparatus for improved etch stop layer or hard mask layer of a memory device

Patent metadata

Field	Value
Publication number	US-2018366386-A1
Application number	US-201715627676-A
Country	US
Kind code	A1
Filing date	Jun 20, 2017
Priority date	Jun 20, 2017
Publication date	Dec 20, 2018
Grant date	—

Abstract

In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

First claim

1 . An apparatus comprising:
an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.

2 . The apparatus of claim 1 , wherein the etch stop layer comprises Aluminum Hafnium Oxide.

3 . The apparatus of claim 1 , wherein the etch stop layer comprises Aluminum Hafnium Silicon Oxide.

4 . The apparatus of claim 1 , wherein the etch stop layer comprises Aluminum Magnesium Hafnium Oxide.

5 . The apparatus of claim 1 , wherein the etch stop layer comprises Aluminum Magnesium Silicon Oxide.

6 . The apparatus of claim 1 , the apparatus further comprising a hard mask comprising Magnesium Oxide.

7 . The apparatus of claim 6 , the hard mask further comprising one or more of Aluminum, Silicon, or Hafnium.

8 . The apparatus of claim 1 , wherein the etch stop layer has a crystallization temperature that is higher than 1000 degrees Celsius.

9 . The apparatus of claim 1 , wherein the etch stop layer has a dry etch rate that is lower than a dry etch rate of Al 2 O 3 .

10 . The apparatus of claim 1 , wherein the apparatus comprises a 3D NAND memory device.

11 . The apparatus of claim 1 , wherein the etch stop layer is a blanket etch stop layer deposited over the entire surface of a wafer.

12 . The apparatus of claim 1 , wherein the etch stop layer comprises a plurality of etch stop portions formed in holes of a dielectric layer formed on a wafer.

13 . A method comprising:
forming an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; depositing a plurality of layers over the etch stop layer; and forming a channel through at least some of the plurality of layers, the channel extending to the etch stop layer.

14 . The method of claim 11 , wherein forming the etch stop layer comprises simultaneously sputtering Aluminum Oxide using a first cathode of a sputtering tool and sputtering one or more of Hafnium Oxide, Silicon Dioxide, or Magnesium Oxide using a second cathode of the sputtering tool.

15 . The method of claim 11 , wherein forming the etch stop layer comprises sputtering a bulk target onto a wafer, the bulk target comprising a combination of Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium.

16 . The method of claim 11 , further comprising forming a hard mask over the plurality of layers, the hard mask comprising Magnesium Oxide.

17 . The method of claim 14 , wherein the hard mask further comprises one or more of Aluminum, Silicon, or Hafnium.

18 . A system comprising:
a semiconductor package comprising:
a first memory chip, the first memory chip comprising:
a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material;
an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and
a channel formed through the tier, the channel extending to the etch stop layer.

19 . The system of claim 16 , further comprising a processor coupled to the semiconductor package.

20 . The system of claim 17 , further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

Assignees

• Intel Corp

Inventors

• Petz Christopher W
• Campbell Philip M
• Ng Wei Yeeng
• Shrotri Kunal Bhaskar
• Keshav Saurabh
• Meldrim John Mark
• Rau Prakash Rau Mokhna
• John Tom Jibu

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69397

  the material containing two or more metal elements · CPC title

• H10P14/69392

  the material containing hafnium, e.g. HfO2 · CPC title