Word line decoder circuitry under a three-dimensional memory array

Patent metadata

Field	Value
Publication number	US-9721663-B1
Application number	US-201615046740-A
Country	US
Kind code	B1
Filing date	Feb 18, 2016
Priority date	Feb 18, 2016
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

First claim

What is claimed is:

1. A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
an array of memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises charge storage regions and a vertical semiconductor channel, and the electrically conductive layers comprise word lines for the memory stack structures;
a word line decoder circuitry including switches for activating a respective word line for the memory stack structures, and located underneath the array of memory stack structures and above the substrate;
a word line vertical interconnection region including multiple sets of at least one conductive interconnection structure, each set of at least one conductive interconnection structure electrically contacting a node of a respective device in the word line decoder circuitry;
bit lines electrically connected to the vertical semiconductor channels through respective drain regions and extending over the array of memory stack structures;
upper-interconnect-level word line connectors extending parallel to the bit lines over a portion of the array of memory stack structures, and electrically connecting a respective set of at least one conductive interconnection structure to the electrically conductive layers; and
at least one element selected from:
a first element of word line contact via structures contacting a respective electrically conductive layer and extending above the alternating stack and contacting a respective upper-interconnect-level word line connector;
a second element of a combination of at least one dielectric material layer overlying the word line decoder circuitry, and a semiconductor material layer overlying the at least one dielectric material layer and underlying the alternating stack; and
a third element of a bit line decoder circuitry including switches for activating a respective bit line for the memory stack structures, located underneath the array of memory stack structures and above the substrate and adjacent to the word line decoder circuitry, and having an areal overlap with the area of the array of memory stack structures in the plan view.

2. The memory device of claim 1 , wherein the memory device comprises the first element.

3. The memory device of claim 2 , wherein the node of the respective device in the word line decoder circuitry is selected from a source region of a field effect transistor, a drain region of a transistor, and a gate electrode of a field effect transistor.

4. The memory device of claim 2 , wherein a set among the sets of at least one conductive interconnection structure comprises:
a stack level connector via structure extending from above a horizontal plane including a top surface of the alternating stack to another horizontal plane including a bottom surface of the alternating stack;
at least one connector metal line underlying the alternating stack; and
at least one connector via structure underlying the alternating stack.

5. The memory device of claim 1 , wherein the memory device comprises the second element.

6. The memory device of claim 5 , wherein the semiconductor material layer comprises horizontal semiconductor channels adjoined to the vertical semiconductor channels of the memory stack structures.

7. The memory device of claim 5 , wherein the array of memory stack structures comprises multiple blocks of memory stack structures that are laterally spaced apart from one another by through-stack contact via structures extending through the alternating stack to a top surface of the semiconductor material layer.

8. The memory device of claim 7 , wherein electrical connection between the word lines and the word line decoder circuitry comprises word line contact via structures contacting a respective electrically conductive layer from above and located between a respective neighboring pair of through-stack contact via structures.

9. The memory device of claim 7 , wherein:
each block of memory stack structures comprises a plurality of clusters of memory stack structures laterally spaced by word line contact via structures contacting a respective electrically conductive layer from above; and
the plurality of clusters of memory stack structures are in a one-dimensional array extending along a horizontal direction parallel to a lengthwise direction of the through-stack contact via structures.

10. The memory device of claim 9 , further comprising at least one feature selected from:
a first feature that each word line contact via structure extending through a same block of memory stack structures contacts a different electrically conductive layer in the alternating stack; and
a second feature that wherein the word line contact via structures extending through a same block of memory stack structures are arranged as a one-dimensional array extending along a horizontal direction parallel to a lengthwise direction of the through-stack contact via structures in a plan view.

11. The memory device of claim 1 , wherein the memory device comprises the third element.

12. The memory device of claim 11 , wherein:
the bit line decoder circuitry has a first rectangular area;
the word line decoder circuitry has a second rectangular area; and
a lengthwise direction of the first rectangular area and a lengthwise direction of the second rectangular area are along a same horizontal direction.

13. The memory device of claim 11 , wherein:
the array of memory stack structures comprises multiple blocks of memory stack structures that are laterally spaced apart by through-stack contact via structures and laterally extending along a lengthwise direction;
vertical electrical connection between the word line decoder circuitry and the electrically conductive layers is provided in a first rectangular region that is laterally offset from an area of the array of memory stack structures and extends along the lengthwise direction; and
vertical electrical connection between the bit line decoder circuitry and the bit lines of the memory stack structures is provided in a second rectangular region that is laterally offset from the area of the memory stack structures and extends along the lengthwise direction.

14. The memory device of claim 13 , further comprising:
an additional array of memory stack structures comprising additional multiple blocks of memory stack structures and laterally spaced from the array of memory stack structures by the second rectangular region; and
a third rectangular region including vertical connection between an additional word line decoder circuitry including switches for activating a respective word line for the memory stack structures of the additional array of memory stack structures, located underneath the additional array of memory stack structures and above the substrate, and having an areal overlap with an area of the additional array of memory stack structures in the plan view,
wherein the second rectangular region comprises vertical electrical connection between bit lines of the additional array of memory stack structures and the bit line decoder circuitry.

15. The memory device of claim 13 , wherein the memory device comprises a periodic repetition of multiple instances of the array of memory stack structures, the first rectangular region, and the second rectangular region.

16. The memory device of claim 1 , wherein the memory device comprises the first feature.

17. The memory device of claim 1 , wherein the memory device comprises the second feature the word line decoder

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Ogawa Hiroyuki
• Toyama Fumiaki
• Ariki Takuya

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C8/10

  Decoders · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title