Through-memory-level via structures for a three-dimensional memory device

Patent metadata

Field	Value
Publication number	US-9818759-B2
Application number	US-201615268946-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Dec 22, 2015
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising: forming at least one in-process alternating stack of insulating layers and sacrificial material layers over a semiconductor substrate;
forming a moat trench including an area of a through-memory-level via region within an outer periphery thereof and backside contact trenches through the at least one in-process alternating stack;
forming a patterned insulating liner layer on sidewalls of the moat trench, while sidewalls of the backside contact trenches are physically exposed to an ambient;

forming at least one through-memory-level opening in the through-memory-level via region;
removing the sacrificial material layers selective to the insulating layers by introducing an etchant through the backside contact trenches, thereby forming backside recesses;
filling the backside recesses with the electrically conductive layer by introducing a reactant through the backside contact trenches, thereby forming the at least one alternating stack;
forming a memory-level assembly located over the semiconductor substrate, the memory-level assembly comprising at least one alternating stack of electrically conductive layers and first portions of insulating layers, and further comprising memory stack structures vertically extending through at least one alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
forming a plurality of laterally-elongated contact via structures through the memory-level assembly, wherein the plurality of laterally-elongated contact via structures laterally extends along a first horizontal direction, and laterally divides the at least one alternating stack into a plurality of laterally spaced-apart blocks within the memory-level assembly; and
forming at least one through-memory-level via structure in the through-memory-level via region in a block, wherein the through-memory-level via region is located between a pair of laterally-elongated contact via structures and between two groups of memory stack structures located in the block and including through-memory-level via structures, wherein each of the at least one through-memory-level via structure vertically extends through the memory-level assembly.

2. The method of claim 1 , further comprising:
forming semiconductor devices located on or over the semiconductor substrate; and
forming lower level metal interconnect structures electrically shorted to nodes of the semiconductor devices and embedded in at least one lower level dielectric layer over the semiconductor substrate, wherein the at least one through-memory-level via structure is formed on the lower level metal interconnect structures.

3. The method of claim 2 , further comprising forming a planar semiconductor material layer over the at least one lower level dielectric layer, wherein the planar semiconductor material layer includes horizontal semiconductor channels connected to vertical semiconductor channels within the memory stack structures.

4. The method of claim 1 , further comprising:
forming at least one through-memory-level opening through the memory-level assembly;
forming an insulating liner around a periphery of each through-memory-level opening; and
forming a through-memory-level via structure on each insulating liner.

5. The method of claim 4 , further comprising:
forming a backside contact trench through the at least one alternating stack concurrently with formation of the at least one through-memory-level opening;
forming an insulating spacer on a sidewall of the backside contact trench concurrent with formation of the at least one insulating liner by depositing and anisotropically etching a conformal insulating material layer,

wherein:
the at least one through-memory-level opening is extended downward while the conformal insulating material layer is anisotropically etched; and
a lower level metal interconnect structure is physically exposed at a bottom of one of the at least one through-memory-level opening.

6. The method of claim 5 , further comprising simultaneously forming a laterally-elongated contact via structure in the backside contact trench and a conductive fill material portion within each insulating liner.

7. The method of claim 1 , further comprising forming a planar semiconductor material layer over the semiconductor substrate, wherein the planar semiconductor material layer includes horizontal semiconductor channels connected to vertical semiconductor channels within the memory stack structures,
wherein:
the through-memory-level via structures extend through an opening in the planar semiconductor material layer;
the plurality of laterally-elongated contact via structures terminates on a top surface of the planar semiconductor material layer; and
the plurality of laterally-elongated contact via structures comprises source lines contacting respective underlying source regions that contact respective horizontal channels located within the planar semiconductor material layer.

8. The method of claim 1 , further comprising:
forming at least one in-process alternating stack of insulating layers and sacrificial material layers over the semiconductor substrate;
forming at least one through-memory-level opening in the through-memory-level via region;
removing the sacrificial material layers selective to the insulating layers to form backside recesses; and
filling the backside recesses with the electrically conductive layer, thereby forming the at least one alternating stack.

9. The method of claim 8 , further comprising:
forming backside contact trenches concurrently with formation of the at least one through-memory-level opening;
concurrently forming an insulating spacer in each of the backside contact trenches and an insulating liner in each of the at least one through-memory-level opening after formation of the electrically conductive layers; and
concurrently forming the at least one through-memory-level via structure and the plurality of laterally-elongated contact via structures.

10. The method of claim 8 , further comprising filling each of the at least one through-memory-level opening with a respective insulating liner and a respective through-memory-level via structure prior to formation of the plurality of laterally-elongated contact via structures.

11. The method of claim 1 , further comprising:
simultaneously forming insulating spacers in the backside contact trenches and the patterned insulating liner in the moat trench; and
simultaneously forming the plurality of laterally-elongated contact via structures on the patterned insulating spacers and a conductive fill material portion on the insulating liner,
wherein a remaining portion of the at least one in-process alternating stack remains within an area enclosed by the moat trench.

12. The method of claim 1 , further comprising:
simultaneously forming insulating spacers in the backside contact trenches and an insulating material fill portion in the moat trench; and
forming the plurality of laterally-elongated contact via structures on the insulating spacers,
wherein a remaining portion of the at least one in-process alternating stack remains within an area enclosed by the moat trench.

13. The method of claim 1 , wherein:
the memory stack structures comprise memory elements of a vertical NAND device;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND device;
the semiconductor substrate comprises a silicon substrate;
the vertical NAND device comprises an array of monolithic

Assignees

• Sandisk Technologies Llc

Inventors

• Kai James
• Liu Jin
• Alsmeier Johann
• Yu Jixin
• Furihata Yoko
• Ogawa Hiroyuki

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title