Gate all around I/O engineering

Patent metadata

Field	Value
Publication number	US-11923441-B2
Application number	US-202217888894-A
Country	US
Kind code	B2
Filing date	Aug 16, 2022
Priority date	Oct 2, 2019
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-κ layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-κ layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.

First claim

What is claimed is:

1. A processing tool for forming a semiconductor device, the processing tool comprising:
a central transfer station having a plurality of processing chambers disposed around the central transfer station;
a robot within the central transfer station configured to move a substrate between the plurality of processing chambers;
a first processing chamber connected to the central transfer station, the first processing chamber configured to perform an enhanced in situ steam generation (eISSG) process to deposit a thermal oxide layer at a pressure below 20 Torr;
a metrology station within the processing tool accessible to the robot, the metrology station comprising one or more of a scatterometer, a refractometer, an ellipsometer, or an e-beam configured to determine a thickness of the thermal oxide layer on a substrate;
a second processing chamber connected to the central transfer station, the second processing chamber configured to perform an atomic layer deposition process;
a third processing chamber connected to the central transfer station, the third processing chamber configured to perform a passivation process and/or a densification process; and
a controller connected to the central transfer station, the robot, the first processing chamber, the metrology station, the second processing chamber, and the third processing chamber, the controller comprising a first configuration to move a substrate on the robot between the plurality of processing chambers and metrology station; a second configuration to perform the enhanced in situ steam generation (eISSG) process to deposit a thermal oxide layer on a substrate in the first processing chamber; a third configuration to perform an analysis to determine the thickness of the thermal oxide layer in the metrology station; a fourth configuration to perform an atomic layer deposition process in the second processing chamber, the atomic layer deposition adjusted for the thickness of the thermal oxide layer, and a fifth configuration to perform the passivation process and/or the densification process.

2. The processing tool of claim 1 , wherein the thermal oxide layer has a thickness in a range of about 3 to about 10 Å.

3. The processing tool of claim 1 , wherein the thermal oxide layer comprises silicon oxide.

4. The processing tool of claim 1 , wherein the atomic layer deposition process comprises depositing a low-K layer on the thermal oxide layer.

5. The processing tool of claim 1 , wherein the atomic layer deposition process is a plasma enhanced atomic layer deposition process.

6. The processing tool of claim 4 , wherein the low-K layer comprises one or more of silicon oxide, silicon oxycarbide, silicon oxynitride, SiCOH, SiCONH, or aluminum oxide.

7. The processing tool of claim 4 , wherein the low-K layer has a dielectric constant in a range of about 1 to about 6.

8. The processing tool of claim 4 , wherein the low-K layer has a thickness of less than about 2 nm.

9. The processing tool of claim 1 , wherein the third processing chamber is configured to perform a passivation process and the passivation process comprises one or more of an annealing process or a plasma treatment process.

10. The processing tool of claim 1 , wherein the third processing chamber is configured to perform a passivation process and the passivation process comprises rapid thermal (RT) annealing the thermal oxide layer with one or more of RTH 2 or RTN 2 .

11. The processing tool of claim 1 , wherein the third processing chamber is configured to perform a passivation process and the passivation process comprises a decoupled plasma (DP) treatment process with one or more of DPHe, DPH 2 , DPN 2 , or DPNH 3 .

12. The processing tool of claim 1 , wherein the third processing chamber is configured to perform a densification process and the densification process comprises rapid thermal (RT) annealing the low-K layer with one or more of RTH 2 or RTN 2 .

13. The processing tool of claim 1 , wherein the third processing chamber is configured to perform a densification process and the densification process comprises a decoupled plasma (DP) treatment process with one or more of DPHe, DPH 2 , DPN 2 , or DPNH 3 .

14. The processing tool of claim 1 , wherein the semiconductor device is a gate-all-around (GAA) transistor.

15. The processing tool of claim 14 , wherein the gate-all-around transistor comprises a source region having a source and a source contact, the source region on a top surface of the substrate; a drain region having a drain and a drain contact, the drain region on the top surface of the substrate; a channel located between the source and the drain and having an axis that that is substantially orthogonal to the top surface of the substrate; a gate enclosing the channel between the source region and the drain region; the thermal oxide layer overlying and in contact with one or more of the gate, the source contact, or the drain contact; and the low-κ layer overlying the thermal oxide layer.

Assignees

• Applied Materials Inc

Inventors

• Hung Steven C H
• Colombeau Benjamin
• Lo Andy
• Lee Byeong Chan
• Swenberg Johanes F
• Guarini Theresa Kramer
• Bevan Malcolm J

Classifications

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6322

  Formation by thermal treatments (formation by plasma treatment H10P14/6319) · CPC title

• H10P14/6309

  of silicon in uncombined form, i.e. pure silicon · CPC title

• H10P14/662 Primary

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10P72/0466

  characterised by the construction of the load-lock chamber · CPC title