Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth

Patent metadata

Field	Value
Publication number	US-9853129-B2
Application number	US-201615242078-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	May 11, 2016
Publication date	Dec 26, 2017
Grant date	Dec 26, 2017

Abstract

A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

First claim

What is claimed is:

1. A method of forming a semiconductor device on a semiconductor substrate, the method comprising:
performing an anisotropic etch process on a semiconductor material to expose a surface in the semiconductor material, wherein the exposed surface is disposed between an existing structure of the semiconductor device and a bulk semiconductor portion of the semiconductor substrate on which the semiconductor material is formed;
performing an isotropic etch process on an exposed sidewall to form a cavity in the semiconductor material that is disposed between the existing structure and the bulk semiconductor portion of the semiconductor substrate; and
forming a layer of deposited material via a selective epitaxial growth (SEG) process on a surface of the cavity, wherein the deposited material includes silicon and an n-type dopant.

2. The method of claim 1 , further comprising performing a pre-epitaxial clean process on the surface of the cavity, wherein the pre-epitaxial clean process includes exposure of the surface of the cavity to hydrogen and fluorine species.

3. The method of claim 2 , wherein exposure of the surface of the cavity further comprises exposing the surface to plasma-excited hydrogen and fluorine species by simultaneously exposing the surface of the cavity to H, NF 3 , and NH 3 plasma-excited species.

4. The method of claim 1 , wherein the isotropic etch process comprises an etch process selective to the semiconductor material.

5. The method of claim 4 , wherein the isotropic etch process comprises a chemical vapor etch process that includes exposing the exposed sidewall to at least one of HCl, HCl and GeH 4 , and Cl 2 .

6. The method of claim 1 , wherein forming the layer of deposited material comprises filling the cavity with the deposited material.

7. The method of claim 1 , further comprising, prior to forming the layer of deposited material, depositing a carbon-containing material on the surface of the cavity, wherein the carbon-containing material includes a silicon-carbon-phosphorus (SiCP) material.

8. The method of claim 7 , wherein the SiCP material includes about 0.1 to 2.0 atomic percent carbon and about 1E10 20 atoms/cm 3 to 1E10 21 atoms/cm 3 phosphorus.

9. The method of claim 1 , wherein performing the isotropic etch process on the exposed sidewall to form the cavity in the semiconductor material comprises removing semiconductor material until a portion of the semiconductor material that comprises a phosphorus-doped bulk semiconductor material is exposed.

10. The method of claim 1 , wherein the n-type dopant comprises arsenic (As), and the selective epitaxial growth (SEG) process includes exposing the surface of the cavity to at least one of AsCl 3 , TBA, or AsH 3 and at least one of dichlorosilane (DCS), HCl, SiH 4 , Si 2 H 6 , or Si 4 H 10 .

11. The method of claim 10 , wherein forming the layer of deposited material comprises filling the cavity with arsenic-doped material having an arsenic concentration sufficient to produce a targeted tensile strain within the deposited material.

12. The method of claim 1 , further comprising forming a layer of additional deposited material via a selective epitaxial growth (SEG) process on a portion of the semiconductor material on which the anisotropic etch process is not performed, wherein the additional deposited material includes silicon (Si) and phosphorus (P).

13. The method of claim 12 , wherein the layer of additional deposited material is formed without exposing the layer of deposited material formed on the surface of the cavity to air.

14. The method of claim 13 , wherein the forming the layer of additional deposited material is performed in a same processing chamber as the forming the layer of deposited material on the surface of the cavity.

Assignees

• Applied Materials Inc

Inventors

• Bauer Matthias
• Gossmann Hans-Joachim Ludwig
• Colombeau Benjamin

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3208

  Silicon carbide · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3442 Primary

  N-type · CPC title