Stacked nanowire devices

Patent metadata

Field	Value
Publication number	US-9484267-B1
Application number	US-201615015347-A
Country	US
Kind code	B1
Filing date	Feb 4, 2016
Priority date	Feb 4, 2016
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

A semiconductor device comprises first stack of nanowires arranged on a substrate comprises a first nanowire and a second nanowire, the second nanowire is arranged substantially co-planar in a first plane with the first nanowire the first nanowire and the second nanowire arranged substantially parallel with the substrate, a second stack of nanowires comprises a third nanowire and a fourth nanowire, the third nanowire and the fourth nanowire arranged substantially co-planar in the first plane with the first nanowire, and the first nanowire and the second nanowire comprises a first semiconductor material and the third nanowire and the fourth nanowire comprises a second semiconductor material, the first semiconductor material dissimilar from the second semiconductor material.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
forming a first layer comprising a first semiconductor material on a substrate,
forming a second layer comprising a second semiconductor material on the first layer,
forming a third layer comprising the first semiconductor material on the second layer,
removing portions of the first layer, the second layer, and the third layer to form a stack of nanowires,
forming a first sacrificial gate stack and a second sacrificial gate stack over the stack of nanowires,
patterning a first mask over the first sacrificial gate stack and a first portion of the stack of nanowires,
removing exposed portions of the second layer,
depositing an insulator material over an exposed second portion of the stack of nanowires,
removing the first mask and the first sacrificial gate stack to expose a first channel region of a portion of the stack of nanowires, and
performing an annealing process.

2. The method of claim 1 , wherein the first semiconductor material is a silicon material and the second semiconductor material is a silicon germanium material.

3. The method of claim 1 , wherein the first semiconductor material is a silicon germanium material and the second semiconductor material is a silicon material.

4. The method of claim 1 , wherein the first semiconductor material is a dissimilar material from the second semiconductor material.

5. The method of claim 1 , wherein the annealing process is operative to drive germanium atoms from the second semiconductor material into the first semiconductor material.

6. The method of claim 1 , further comprising:
covering the first channel region,
removing the insulator material from the second portion of the stack of nanowires, and
performing an epitaxial growth process to form a source/drain region on the second portion of the second stack of nanowires.

7. The method of claim 6 , further comprising:
removing the second gate sacrificial stack to expose a second channel region of a portion of the stack of nanowires,
exposing the first channel region,
forming a first gate stack on the first channel region, and
forming a second gate stack on the second channel region.

8. The method of claim 1 , further comprising depositing a liner layer over the exposed second portion of the stack of nanowires prior to depositing the insulator material over an exposed second portion of the stack of nanowires.

9. The method of claim 1 , further comprising forming a second mask over the second sacrificial gate stack prior to removing the first mask and the first sacrificial gate stack to expose the first channel region of the portion of the stack of nanowires.

10. A method for fabricating a semiconductor device, the method comprising:
forming a first layer comprising a first semiconductor material on a substrate,
forming a second layer comprising a second semiconductor material on the first layer,
forming a third layer comprising the first semiconductor material on the second layer,
removing portions of the first layer, the second layer, and the third layer to form a stack of nanowires,
forming a first sacrificial gate stack and a second sacrificial gate stack over the stack of nanowires,
removing exposed portions of the second layer,
depositing an insulator material over exposed portions of the stack of nanowires,
patterning a first mask over the first sacrificial gate stack and a first portion of the stack of nanowires,
removing exposed insulator material from a second portion of the stack of nanowires,
epitaxially growing a first source/drain region on the second portion of the stack of nanowires, and
performing an annealing process operative to drive atoms from the first source/drain region into a second channel region.

11. The method of claim 10 , further comprising:
patterning a second mask over the second sacrificial gate stack and the first source/drain region,
removing exposed insulator material from the first portion of the stack of nanowires, and
epitaxially growing a second source/drain region on the first portion of the stack of nanowires.

12. The method of claim 11 , further comprising removing the first sacrificial gate stack and the second sacrificial gate stack to expose a first channel region and a second channel region.

13. The method of claim 11 , further comprising removing exposed insulator material from the first channel region and the second channel region.

14. The method of claim 11 , further comprising:
forming a first gate stack on a first channel region, and
forming a second gate stack on the second channel region.

15. The method of claim 11 , wherein the first semiconductor material is a silicon material and the second semiconductor material is a silicon germanium material.

16. The method of claim 11 , wherein the first semiconductor material is a silicon germanium material and the second semiconductor material is a silicon material.

17. The method of claim 11 , wherein the first semiconductor material is a dissimilar material from the second semiconductor material.

18. The method of claim, 11 , wherein the second source/drain region include silicon germanium.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Divakaruni Ramachandra
• Li Juntao

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/14

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title