Semiconductor package

Patent metadata

Field	Value
Publication number	US-11923342-B2
Application number	US-202217705872-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Jul 11, 2019
Publication date	Mar 5, 2024
Grant date	Mar 5, 2024

Abstract

A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

First claim

What is claimed is:

1. A semiconductor package comprising:
a lower semiconductor package,
wherein the lower semiconductor package includes:
a first semiconductor device including a first through electrode;
a second semiconductor device on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
a lower molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device; and
an upper redistribution layer on the second semiconductor device and electrically connected to the second through electrode,
wherein an upper surface of the second through electrode is in contact with a lower surface of the upper redistribution layer, and
wherein the upper surface of the second through electrode and an upper surface of the lower molding member are coplanar with one another.

2. The semiconductor package according to claim 1 , wherein a sidewall of the lower molding member is aligned with a sidewall of the upper redistribution layer.

3. The semiconductor package according to claim 1 , wherein the lower semiconductor package further includes:
a first pad on the first through electrode;
a second pad under the second through electrode;
a connection bump between the first pad and the second pad; and
a connection layer between the first semiconductor device and the second semiconductor device and covering the first pad, the second pad, and the connection bump.

4. The semiconductor package according to claim 1 , wherein a sidewall of the second semiconductor device is positioned farther inward than a sidewall of the first semiconductor device.

5. The semiconductor package according to claim 1 , further comprising an upper semiconductor package on the lower semiconductor package, and
wherein the upper semiconductor package includes:
a third semiconductor device;
a connection terminal electrically connected to the third semiconductor device and the upper redistribution layer;
an upper molding member covering a sidewall of the third semiconductor device; and
a heat sink on the upper molding member, and
wherein a sidewall of the upper molding member is aligned with a sidewall of the lower semiconductor package.

6. The semiconductor package according to claim 1 , wherein the lower semiconductor package further includes:
a first protection layer on the first semiconductor device and covering an upper portion of the first through electrode; and
a second protection layer on the second semiconductor device and covering an upper portion of the second through electrode,
wherein an upper surface of the second protection layer is coplanar with the upper surface of the second through electrode.

7. A semiconductor package comprising:
a lower package; and
an upper package on the lower package,
wherein the lower package includes:
a first semiconductor device including a first through electrode;
a second semiconductor device on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
a lower molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device;
an upper redistribution layer on the second semiconductor device and electrically connected to the second through electrode;
a lower redistribution layer below the first semiconductor device and electrically connected to the first through electrode; and
an external connection terminal electrically connected to the lower redistribution layer,
wherein the upper package includes:
a third semiconductor device; and
a first connection terminal electrically connected to the third semiconductor device and the upper redistribution layer,
wherein an upper surface of the second through electrode is in contact with a lower surface of the upper redistribution layer, and
wherein the upper surface of the second through electrode and an upper surface of the lower molding member are coplanar with one another.

8. The semiconductor package according to claim 7 , wherein the lower molding member is free of a through electrode.

9. The semiconductor package according to claim 7 , wherein a sidewall of the lower molding member is aligned with a sidewall of the lower redistribution layer.

10. The semiconductor package according to claim 7 , wherein a sidewall of the second semiconductor device is located farther inward than a sidewall of the first semiconductor device.

11. The semiconductor package according to claim 7 , wherein the upper package further includes:
an upper molding member that covers the third semiconductor device; and
a heat sink on the upper molding member and the third semiconductor device.

12. The semiconductor package according to claim 7 , wherein a sidewall of the upper package is located farther inward than a sidewall of the lower molding member.

13. The semiconductor package according to claim 7 ,
wherein the upper redistribution layer comprises:
a redistribution pattern that is electrically connected to the second through electrode; and
an insulation region that is on the redistribution pattern, and

wherein the upper surface of the lower molding member contacts only the insulation region of the upper redistribution layer.

14. A semiconductor package comprising:
a first semiconductor device including a first through electrode;
a second semiconductor device on the first semiconductor device and including a second through electrode electrically connected to the first through electrode;
a lower molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, wherein the lower molding member is spaced apart from the first and second through electrodes;
an upper redistribution layer on the second semiconductor device and including an upper redistribution pattern electrically connected to the second through electrode; and
a third semiconductor device on the upper redistribution layer and electrically connected to the upper redistribution pattern,
wherein an upper surface of the second through electrode and an upper surface of the lower molding member are in contact with a lower surface of the upper redistribution layer.

15. The semiconductor package according to claim 14 , further comprising:
a circuit substrate including an upper pad and a lower pad electrically connected to the upper pad; and
an external connection terminal electrically connected to the lower pad.

16. The semiconductor package according to claim 15 , wherein a sidewall of the lower molding member is aligned with a sidewall of the circuit substrate.

17. The semiconductor package according to claim 14 , further comprising:
a lower redistribution layer below the first semiconductor device and electrically connected to the first through electrode; and
an external terminal electrically connected to the lower redistribution layer.

18. The semiconductor package according to claim 14 , further comprising:
a first pad on the first through electrode;
a second pad under the second through electrode;
a connection bump between the first pad and the second pad; and
a connection layer between the first semiconductor device and the second semiconductor device, and covering the first pad, the second pad, and the connection bump.

19. The semiconductor package according to claim 14 , wherein a sidewall of the second semiconductor device is located farther inward than a sidewall of the fir

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Sanguk
• Jo Chajea
• Kim Hyoeun
• Seo Sunkyoung

Classifications

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title