Three dimensional integrated circuits stacking approach

Patent metadata

Field	Value
Publication number	US-9502380-B2
Application number	US-201514959094-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Sep 28, 2012
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures.

First claim

What is claimed is:

1. A method of forming a semiconductor package, comprising:
placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate, wherein connection structures are arranged along a first surface of the interposer facing the first adhesive layer;
forming a first molding compound over the first adhesive layer and the interposer, and laterally surrounding the interposer;
removing a portion of the first molding compound to expose the TSVs along a second surface of the interposer;
forming a first redistribution structure over the second surface of the interposer and the first molding compound;
forming conductive bump structures over the first redistribution structure; and
bonding a first packaged die to the conductive bump structures.

2. The method of claim 1 , further comprising:
forming a second molding compound over the first redistribution structure and the first packaged die.

3. The method of claim 2 , further comprising:
removing the first carrier substrate and the first adhesive layer;
attaching the second molding compound to a second carrier substrate by way of a tape that is separated from the first redistribution structure by the first packaged die;
removing a portion of a protective layer, which is located on the first surface of the interposer, to expose the connection structures of the interposer; and
forming external connectors over the connection structures of the interposer.

4. The method of claim 2 , further comprising:
removing the first carrier substrate and the first adhesive layer to expose the connection structures of the interposer.

5. The method of claim 4 , further comprising:
forming a second redistribution structure electrically coupled to the connection structures of the interposer and separated from the first redistribution structure by way of the first molding compound.

6. The method of claim 5 , further comprising:
attaching the second molding compound to a second carrier die by way of a second adhesive layer prior to forming the second redistribution structure.

7. The method of claim 1 , further comprising:
forming an underfill laterally surrounding the conductive bump structures at a position vertically between the first packaged die and the first redistribution structure.

8. The method of claim 1 , wherein the first packaged die has a sidewall that is laterally offset from a sidewall of the interposer.

9. The method of claim 1 , further comprising:
bonding a second packaged die bonded to the first redistribution structure, wherein the first packaged die is separated from the second packaged die by a space that is free of the first packaged die.

10. The method of claim 1 , further comprising:
removing a portion of the interposer to expose the TSVs along the second surface of the interposer.

11. The method of claim 10 , wherein removing the portion the first molding compound is performed by a grinding process, a chemical-mechanical polishing process, or an etching process.

12. A method of forming a semiconductor package, comprising:
placing an interposer with one or more TSVs on an adhesive layer overlying a carrier substrate, wherein connection structures are arranged along a first surface of the interposer facing the adhesive layer;
forming a first molding compound surrounding the interposer, wherein the first molding compound is arranged to expose the TSVs along a second surface of the interposer;
forming conductive bump structures over the second surface of the interposer, wherein the conductive bump structures are electrically coupled to the TSVs;
bonding a first packaged die to the conductive bump structures, wherein an edge of the first packaged die is beyond an edge of the interposer; and
removing the carrier substrate and the adhesive layer.

13. The method of claim 12 , further comprising:
bonding a second packaged die to the conductive bump structures, wherein the first packaged die is separated from the second packaged die by a space that is free of the first packaged die.

14. The method of claim 12 , further comprising:
forming a first redistribution structure over the second surface of the interposer and the first molding compound; and
forming the conductive bump structures over the first redistribution structure at locations laterally offset from the interposer.

15. The method of claim 12 , further comprising:
forming at least one metal post on the first surface of the interposer, wherein the at least one metal post is electrically connected to a TSV of the one or more TSVs.

16. The method of claim 15 , further comprising:
forming a protective layer surrounding sidewalls of the at least one metal post, wherein the protective layer laterally separates the at least one metal post from the first molding compound.

17. A method of forming a semiconductor package, comprising:
placing an interposer with one or more TSVs on an adhesive layer overlying a carrier substrate, wherein connection structures are arranged along a first surface of the interposer facing the adhesive layer;
forming a first molding compound surrounding the interposer, wherein the first molding compound is arranged to expose the TSVs along a second surface of the interposer;
forming a plurality of conductive bump structures, which are electrically coupled to the TSVs, over the second surface of the interposer;
bonding a first packaged die to a first set of the plurality of conductive bump structures, so that one edge of the first packaged die is beyond a first edge of the interposer; and
bonding a second packaged die to a second set of the plurality of conductive bump structures, so that one edge of the second packaged die is beyond a second edge of the interposer opposite the first edge.

18. The method of claim 17 , further comprising:
forming a second molding compound over the interposer, the first packaged die, and the second packaged die.

19. The method of claim 17 , further comprising:
removing the carrier substrate and the adhesive layer to expose the connection structures along the first surface of the interposer.

20. The method of claim 17 , further comprising:
forming the first molding compound over the interposer and over the adhesive layer; and
removing a portion the first molding compound and a portion of the interposer to expose the TSVs along the second surface of the interposer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Hou Shang-Yun

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title