Methods of manufacturing semiconductor packages

Patent metadata

Field	Value
Publication number	US-10141286-B2
Application number	US-201715499229-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	Aug 24, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

Methods of manufacturing a semiconductor package are provided. The methods may include manufacturing a semiconductor chip in a first semiconductor manufacturing environment and mounting the semiconductor chip on an upper surface of a printed circuit board. The method may also include forming a molding member in a second semiconductor manufacturing environment that is different from the first semiconductor manufacturing environment, forming a capping member including a material different from the molding member and covering an exposed outer surface of the molding member, and attaching a carrier substrate onto the capping member. The semiconductor chip may be between the printed circuit board and the carrier substrate. The method may further include forming a redistribution line layer on a lower surface of the printed circuit board in a third semiconductor manufacturing environment, forming an external connection member on the redistribution line layer, and removing the carrier substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, the method comprising:
manufacturing a semiconductor chip in a first semiconductor manufacturing environment;
mounting the semiconductor chip on an upper surface of a printed circuit board, the printed circuit board comprising a lower surface opposite the upper surface;
forming a molding member on the semiconductor chip in a second semiconductor manufacturing environment different from the first semiconductor manufacturing environment;
forming a capping member comprising a material different from the molding member and covering an exposed outer surface of the molding member;
attaching a carrier substrate onto the capping member, the semiconductor chip being between the printed circuit board and the carrier substrate;
forming a redistribution line layer on the lower surface of the printed circuit board in a third semiconductor manufacturing environment different from the second semiconductor manufacturing environment, the redistribution line layer being electrically connected to the semiconductor chip;
forming an external connection member on the redistribution line layer; and
removing the carrier substrate.

2. The method of claim 1 , wherein cleanliness of the first semiconductor manufacturing environment and the third semiconductor manufacturing environment is higher than that of the second semiconductor manufacturing environment.

3. The method of claim 1 , wherein the capping member covers an entirety of the exposed outer surface of the molding member.

4. The method of claim 1 , wherein the capping member comprises a silicon oxide film, a silicon nitride film and/or a silicon oxynitride film.

5. The method of claim 1 , further comprising removing the capping member after removing the carrier substrate.

6. The method of claim 1 , wherein the capping member covers side surfaces of the printed circuit board.

7. The method of claim 1 , wherein the semiconductor chip comprises a plurality of semiconductor chips, and
at least one of the plurality of semiconductor chips comprises a through silicon via.

8. The method of claim 1 , wherein the external connection member comprises a solder ball and/or a solder bump.

9. A method of manufacturing a semiconductor package, the method comprising:
manufacturing a first semiconductor chip;
mounting the first semiconductor chip on a substrate;
forming a first molding member covering side surfaces of the first semiconductor chip;
forming a capping member comprising a material different from the first molding member and covering the first molding member and an upper surface of the first semiconductor chip; and
forming a redistribution line layer on the capping member, the redistribution line layer being electrically connected to the first semiconductor chip,
wherein the capping member covers an entirety of an exposed outer surface of the first molding member.

10. The method of claim 9 , wherein forming the redistribution line layer comprises forming a contact hole in a portion of the capping member, and the contact hole does not expose the first molding member.

11. The method of claim 9 , wherein the first semiconductor chip is a wafer level package.

12. The method of claim 9 , further comprising mounting a second semiconductor chip on the redistribution line layer,
wherein the second semiconductor chip is of a different type from the first semiconductor chip.

13. The method of claim 12 , further comprising forming a second molding member covering side surfaces of the second semiconductor chip after mounting the second semiconductor chip.

14. The method of claim 13 , wherein a coefficient of thermal expansion of the first molding member is different from that of the second molding member.

15. A method of manufacturing a semiconductor package, the method comprising:
mounting a semiconductor chip on a first surface of a substrate, the substrate comprising a second surface opposite the first surface;
forming a molding layer on the semiconductor chip;
forming a capping layer entirely covering an exposed outer surface of the molding layer, the capping layer comprising a material different from the molding layer;
attaching a carrier substrate to the capping layer, the semiconductor chip being between the substrate and the carrier substrate; and
forming a redistribution line layer on the second surface of the substrate after forming the capping layer.

16. The method of claim 15 , wherein the substrate comprises a printed circuit board, and
wherein the redistribution line layer is electrically connected to the semiconductor chip.

17. The method of claim 15 , wherein the capping layer comprises a silicon oxide film, a silicon nitride film and/or a silicon oxynitride film.

18. The method of claim 17 , wherein the capping layer covers a side of the substrate.

19. The method of claim 17 , wherein forming the molding layer and forming the capping layer are performed in a first environment having a first level of cleanliness, and
wherein forming the redistribution line layer is performed in a second environment having a second level of cleanliness that is higher than the first level of cleanliness.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Won-Il
• Jo Cha-Jea
• Kim Ji-Hwang

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W72/0198

  batch processes · CPC title