Power module and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10051742-B2
Application number	US-201514964575-A
Country	US
Kind code	B2
Filing date	Dec 10, 2015
Priority date	Dec 10, 2015
Publication date	Aug 14, 2018
Grant date	Aug 14, 2018

Abstract

A power module and a manufacturing method thereof are provided, and the power module includes a carrier substrate, an interconnection layer, a first chip, a second chip, a ceramic bonding substrate, a top interconnection layer and a lead frame. The interconnection layer is disposed on the carrier substrate. The first chip and the second chip are disposed on the interconnection layer, and electrically connected to the interconnection layer. The ceramic bonding substrate is disposed on the interconnection layer, and is disposed in between the first chip and the second chip so as to separate the first chip from the second chip. The top interconnection layer is disposed on the ceramic bonding substrate, covers the first chip and the second chip, and is electrically connected to the first chip and the second chip. The lead frame is disposed on the top interconnection layer and electrically connected to the top interconnection layer.

First claim

What is claimed is:

1. A power module, comprising:
a carrier substrate;
an interconnection layer, disposed on the carrier substrate, wherein the interconnection layer comprises an insulating layer and a conductive patterned structure located within the insulating layer;
a first chip and a second chip, disposed on the interconnection layer, wherein the first chip and the second chip are electrically connected to the interconnection layer, and the conductive patterned structure of the interconnection layer extends from a position where the first chip and the second chip are disposed to another position that does not overlap with the position of the first chip and the second chip, such that the conductive patterned structure is extended to outside of an outline of the first chip and the second chip, and used as a redistribution layer, and the first chip is a power chip;
a ceramic bonding substrate, disposed on the interconnection layer and disposed in between the first chip and the second chip so as to separate the first chip from the second chip;
a top interconnection layer, disposed on the ceramic bonding substrate and covers the first chip and the second chip, wherein the top interconnection layer is electrically connected to the first chip and the second chip;
a lead frame, disposed on the top interconnection layer and electrically connected to the top interconnection layer; and
a molding material layer, disposed on the lead frame.

2. The power module according to claim 1 , further comprising a conductive structure penetrating the ceramic bonding substrate, wherein the conductive structure is electrically connected to the interconnection layer and the top interconnection layer respectively.

3. The power module according to claim 1 , wherein:
a gap exists in between the first chip and the ceramic bonding substrate and in between the second chip and the ceramic bonding substrate respectively, and the top interconnection layer further comprises an insulating layer and a conductive patterned structure located within the insulating layer, wherein the insulating layer fills into the gap.

4. The power module according to claim 1 , further comprising a heat dissipation metal layer disposed on a bottom surface of the carrier substrate.

5. A power module, comprising:
a carrier substrate;
a bottom interconnection layer, disposed on the carrier substrate;
a first bottom chip and a second bottom chip, disposed on the bottom interconnection layer, wherein the first bottom chip and the second bottom chip are electrically connected to the bottom interconnection layer; and
a bottom ceramic bonding substrate, disposed on the bottom interconnection layer and disposed in between the first bottom chip and the second bottom chip so as to separate the first bottom chip from the second bottom chip, and
a first interconnection layer disposed on the bottom ceramic bonding substrate, the first bottom chip and the second bottom chip;
an interconnection layer, disposed on the carrier substrate;
a first chip and a second chip, disposed on the interconnection layer, wherein the first chip and the second chip are electrically connected to the interconnection layer;
a ceramic bonding substrate, disposed on the interconnection layer and disposed in between the first chip and the second chip so as to separate the first chip from the second chip;
a top interconnection layer, disposed on the ceramic bonding substrate and covers the first chip and the second chip, wherein the top interconnection layer is electrically connected to the first chip and the second chip;
a lead frame, disposed on the top interconnection layer and electrically connected to the top interconnection layer; and
a molding material layer, disposed on the lead frame.

6. The power module according to claim 5 , wherein the carrier substrate is a metal core substrate, and the metal core substrate comprises a metal core layer and an insulating dielectric layer.

7. The power module according to claim 5 , further comprising a conductive structure penetrating through the bottom ceramic bonding substrate, wherein the conductive structure is electrically connected to the bottom interconnection layer and the first interconnection layer respectively.

8. The power module according to claim 5 , wherein:
a gap exists in between the first bottom chip and the bottom ceramic bonding substrate and in between the second bottom chip and the bottom ceramic bonding substrate respectively, and
the first interconnection layer comprises an insulating layer and a conductive patterned structure located within the insulating layer, wherein the insulating layer fills into the gap.

9. A package structure, comprising:
a carrier substrate;
an interconnection layer, disposed on the carrier substrate, wherein the interconnection layer comprises an insulating layer and a conductive patterned structure located within the insulating layer; and
a first chip and a second chip, disposed on the interconnection layer, wherein the first chip and the second chip are electrically connected to the interconnection layer, and the conductive patterned structure of the interconnection layer at least extends from a position where the first chip or the second chip is disposed to another position that does not overlap with the position of the first chip or the second chip, such that the conductive patterned structure is extended to outside of an outline of the first chip or the second chip, and used as a redistribution layer, and the first chip is a power chip.

10. The package structure according to claim 9 , further comprising:
a ceramic bonding substrate, disposed on the interconnection layer and disposed in between the first chip and the second chip so as to separate the first chip from the second chip.

11. The package structure according to claim 10 , further comprising:
a top interconnection layer, disposed on the ceramic bonding substrate and covering the first chip and the second chip, wherein the top interconnection layer is electrically connected to the first chip and the second chip.

12. The package structure according to claim 11 , further comprising
a lead frame, disposed on the top interconnection layer and electrically connected to the top interconnection layer; and
a molding material layer, disposed on the lead frame.

13. The package structure according to claim 11 , further comprising a conductive structure penetrating the ceramic bonding substrate, wherein the conductive structure is electrically connected to the interconnection layer and the top interconnection layer respectively.

14. The package structure according to claim 11 , wherein:
a gap exists in between the first chip and the ceramic bonding substrate and in between the second chip and the ceramic bonding substrate respectively, and the top interconnection layer further comprises an insulating layer and a conductive patterned structure located within the insulating layer, wherein the insulating layer fills into the gap.

15. The package structure according to claim 9 , further comprising:
a bottom interconnection layer, disposed on the carrier substrate;
a first bottom chip and a second bottom chip, disposed on the bottom interconnection layer, wherein the first bottom chip and the second bottom chip are electrically connected to the bottom interconnection layer; and
a bottom ceramic bonding substrate, disposed on the bottom interconnection layer and disposed in between the first bottom chip and the second bottom chip so as to separate the first bottom chip from the second bottom chip, and
a first interconnection layer

Assignees

• Ind Tech Res Inst

Inventors

• Yang Shu-Jung
• Chao Yu-Lin
• Chien Heng-Chieh
• Liu Chun-Kai

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title