Semiconductor and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-11917815-B2
Application number	US-202318123736-A
Country	US
Kind code	B2
Filing date	Mar 20, 2023
Priority date	Aug 29, 2019
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor device, the method comprising:
defining an active region by forming a device isolation layer in a substrate by using a first mask;
forming a trench in the substrate crossing the active region and extending in a first direction, and by applying an insulating layer to form a first conductive layer filling a bottom portion of the trench, forming a buried word line;
forming a second mask filling a top portion of the trench on the word line;
by using the first mask and the second mask, recessing the device isolation layer such that side surfaces of a top portion of the active region are exposed;
forming a mask pattern exposing the first mask of a portion corresponding to the center of the active region, and by using the mask pattern, forming a contact hole by removing the exposed first mask and a top portion of the active region under the first mask;
forming a stop insulating layer and a gap fill insulating layer on an entire surface of the substrate, and by removing a portion of the gap fill insulating layer, forming a buffer insulating layer filling a space between two first masks adjacent to each other in the first direction;
forming a first contact by filling the contact hole with a second conductive layer; and
forming a bit line extending in a second direction perpendicular to the first direction on the word line, the bit line being connected to the first contact,
wherein the active region has a shape extending in an oblique direction with respect to the first direction, and
wherein the first contact is self-aligned to the active region by the first mask and the second mask that are arranged around the contact hole.

2. The method of claim 1 , wherein:
the semiconductor device comprises a cell region in which the active region of a bar shape is defined, and a core region around the cell region,
the method further comprising: before the forming of the word line,
forming a first protective mask covering the cell region; and
by using the first protective mask, removing the first mask on the core region.

3. The method of claim 1 , wherein:
in the forming of the second mask, a top surface of the second mask is formed to have a height equal to or greater than a top surface of the active region and equal to or less than a top surface of the first mask.

4. The method of claim 1 , wherein:
the semiconductor device comprises a cell region in which the active region having a bar shape is included, and a core region around the cell region,
the method further comprising: before the recessing of the device isolation layer,
forming a third mask on the entire surface of the substrate;
forming a protective mask covering the core region; and
by using the protective mask, removing the third mask on the cell region.

5. The method of claim 1 , wherein:
in the forming of the contact hole, the contact hole is formed to have a shape in which a width thereof in the oblique direction narrows toward a bottom portion thereof, and
the active region is exposed at a bottom portion of the contact hole.

6. The method of claim 5 , wherein:
the mask pattern is removed in an ashing process, and
after the mask pattern is removed, a width of the contact hole in the first direction corresponds to, when at least three active regions are arranged in the first direction, a distance between a first one of the active regions and a third one of the active regions, wherein the second one of the active regions is between the first and third ones of the active regions.

7. The method of claim 1 , wherein:
in the forming of the contact hole, the mask pattern is formed as any one shape of a circular type, an elliptical type, a parallelogram type, and a line type, and
in the forming of the first contact, a shape of a top surface of the first contact is determined according to the shape of the mask pattern.

8. The method of claim 1 , further comprising:
after the forming of the buffer insulating layer, forming a spacer covering side surfaces of the first mask and the active region under the first mask.

9. The method of claim 1 , wherein the forming of the first contact comprises:
cleaning the entire surface of the substrate;
forming a third conductive layer on the entire surface of the substrate; and
planarizing the third conductive layer such that the third conductive layer remains only in the contact hole, as a contact.

10. The method of claim 9 , further comprising: after the forming of the first contact,
forming a fourth conductive layer on the entire surface of the substrate; and
by patterning the fourth conductive layer, forming pass conductive layers extending in the second direction, covering the first contact, and being apart from each other in the first direction.

11. The method of claim 10 , wherein:
the semiconductor device comprises a cell region in which the active region having a bar shape is formed, and a core region around the cell region, and
when the pass conductive layers are formed, a gate electrode layer of a transistor of the core region is also formed.

12. A manufacturing method of a semiconductor device, the method comprising:
defining an active region by forming a device isolation layer in a substrate by using a first mask;
forming a trench in the substrate crossing the active region and extending in a first direction, and by filling a bottom portion of the trench with a single metal layer, forming a buried word line;
forming a second mask filling a top portion of the trench on the word line;
by using the first mask and the second mask, recessing the device isolation layer such that side surfaces of a top portion of the active region are exposed;
forming a mask pattern exposing the first mask of a portion corresponding to the center of the active region, and by using the mask pattern, forming a contact hole by removing the exposed first mask and a top portion of the active region under the first mask;
forming a gap fill insulating layer on an entire surface of the substrate, and by removing a portion of the gap fill insulating layer, forming a buffer insulating layer filling a space between two first masks adjacent to each other in the first direction;
forming a contact by filling the contact hole with a first conductive layer; and
forming a bit line extending in a second direction perpendicular to the first direction on the word line, the bit line being connected to the contact.

13. The method of claim 12 , wherein the single metal layer comprises TiN.

14. The method of claim 12 , wherein:
in the forming of the contact hole, the contact hole is formed to have a shape in which a width thereof in an oblique direction narrows toward a bottom portion thereof,
the active region is exposed at a bottom portion of the contact hole, and
the contact is self-aligned to the active region by the first mask and the second mask.

15. The method of claim 12 , wherein:
in the forming of the contact hole, the mask pattern is formed as any one shape of a circular type, an elliptical type, a parallelogram type, and a line type, and
in the forming of the contact, a shape of a top surface of the contact is determined according to the shape of the mask pattern.

16. The method of claim 12 , further comprising: after the forming of the contact, forming a second conductive layer on the entire surface of the substrate; and
by patterning the second conductive layer, forming pass conductive layers extending in the second direction, covering the contact, and being apart from each other in the first direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyosub
• Kim Keunnam
• Kim Dongoh
• Kim Bongsoo
• Kim Euna
• Yoon Chansic
• Lee Kiseok
• Jung Hyeonok
• Han Sunghee
• Hwang Yoosang

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• H10W20/098

  by filling between adjacent conductive parts · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/086

  involving buried masks · CPC title