Semiconductor devices and methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-9478548-B2
Application number	US-201514639360-A
Country	US
Kind code	B2
Filing date	Mar 5, 2015
Priority date	Aug 4, 2014
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary isolation pattern to define a plurality of active patterns of a substrate that are spaced apart from each other, each of the active patterns having a first contact region at a central portion thereof and second and third contact regions at edge portions thereof on opposite sides of the central portion, respectively;
forming buried gate structures in upper portions of the preliminary isolation pattern and the active patterns, each of the buried gate structures extending in a first direction;
forming a first insulation layer on the preliminary isolation pattern and the active patterns;
etching away a portion of the first insulation layer on the first contact region of one of the active patterns and an upper portion of the first contact region thereunder to form a preliminary first opening having a bottom at which the first contact region is exposed and sides at which an upper portion of preliminary the isolation pattern defining the first contact region is exposed;
etching away said upper portion of the preliminary isolation pattern exposed at the sides of the preliminary first opening such that two of the active patterns adjacent to opposites sides of said one of the active patterns, respectively, in the first direction and two of the buried gate structures adjacent one another in a second direction are exposed, and to thereby form a second opening, the second opening exposing a side surface of each of said two of the active patterns in the first direction and exposing said two of the buried gate structures in the second direction;
forming an insulation pattern along sides of the second opening; and
forming a wiring structure contacting the first contact region in the second opening.

2. The method of claim 1 , wherein the buried gate structures are formed to divide the first, second and the third contact regions from each other in each of the active patterns.

3. The method of claim 1 , wherein each of the active patterns extends in a third direction that is not perpendicular to the first direction, and wherein the first contact region of each of the active patterns is disposed in a space delimited by side surfaces of the active patterns and sides of two of the buried gate structures adjacent one another in the second direction, and wherein the second direction is substantially perpendicular to the first direction.

4. The method of claim 1 , wherein etching the preliminary isolation pattern exposed at the sides of the preliminary first opening to form the second opening is carried out by an isotropic etching process.

5. The method of claim 1 , wherein forming the insulation pattern includes:
forming a second insulation layer along surfaces defining the second opening and on the first insulation layer to electrically insulate the active patterns from the buried gate structures; and
anisotropically etching the second insulation layer.

6. The method of claim 5 , wherein the second insulation layer is formed of silicon nitride, silicon oxynitride or silicon oxide.

7. The method of claim 1 , further comprising forming a first conductive layer on the first insulation layer.

8. The method of claim 1 , wherein forming the wiring structure includes:
forming a conductive layer to fill the second opening; and
etching away one part of the conductive layer while leaving a remaining part of the conductive layer as the wiring structure inside the second opening.

9. The method of claim 1 , wherein an upper portion of the wiring structure is formed to have a linear shape extending in the second direction and the second direction is substantially perpendicular to the first direction.

10. The method of claim 1 , wherein forming the preliminary first opening includes:
forming an etching mask having segments that are spaced apart from each other on the first insulation layer, each of the segments overlapping the second and third contact regions of respective ones of the active patterns adjacent to one another in the first direction and a portion of the isolation pattern adjacent to the second and third contact regions; and
etching the first insulation layer using the etching masks.

11. The method of claim 1 , wherein forming the preliminary first opening includes:
forming an etching mask on the first insulation layer, the etching mask having a hole therethrough exposing the first contact region of each of the active patterns; and
etching the first insulation layer using the etching mask.

12. The method of claim 1 , wherein the insulation pattern is formed in the second opening directly on the side surfaces of said two of the active patterns exposed in the first direction and directly on the two buried gate structures exposed in the second direction.

13. A method of manufacturing a semiconductor device, the method comprising:
forming a preliminary isolation pattern to define a plurality of active patterns of a substrate, each of the active patterns including a contact region;
forming buried gate structures in upper portions of the active patterns and the preliminary isolation pattern, each of the buried gate structures extending in a first direction;
forming a first insulation layer on the preliminary isolation pattern and the active patterns;
etching away a portion of the first insulation layer on the contact region of a respective one of the active regions and an upper portion of the contact region thereunder to form a preliminary first opening having a bottom at which the contact region is exposed and sides at which an upper portion of preliminary the isolation pattern defining the contact region is exposed;
subsequently performing an isotropic etching process to etch an upper portion of the isolation pattern exposed at the sides of the preliminary first opening and to thereby form a second opening, the second opening having a width in the first direction greater than that of the preliminary first opening at a level of an upper surface of the contact region;
forming an insulation pattern along sides of the second opening; and
forming a wiring structure contacting the contact region in the second opening.

14. The method of claim 13 , wherein the isotropic etching process of etching the upper portion of the isolation pattern exposed at the sides of the preliminary first opening to form the second opening etches away the upper portion of the isolation pattern so that a side surface of each of two of the active patterns adjacent opposite sides of said one of the active patterns, respectively, in the first direction are exposed at opposite sides of the second opening.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Do-Yeong
• Yoon Chan-Sic
• Lee Ki-Seok
• Jung Hyeon-Ok

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6927

  the material being a silicon oxynitride, e.g. SiON or SiON:H · CPC title