Method of forming active patterns, active pattern array, and method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9634012-B2
Application number	US-201615015651-A
Country	US
Kind code	B2
Filing date	Feb 4, 2016
Priority date	Jul 20, 2015
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.

First claim

What is claimed is:

1. A method of forming active patterns, the method comprising:
forming a plurality of first patterns in a first direction on a cell region of a substrate and a second pattern on a peripheral circuit region of the substrate, each of the first patterns extending in a third direction crossing the first direction;
forming a plurality of first masks in the first direction on the first patterns and a second mask on the second pattern, each of the first masks extending in a fourth direction crossing the third direction;
forming a plurality of third masks between the first masks, each of the third masks extending in the fourth direction;
etching the first patterns using the first and third masks as an etching mask and the second pattern using the second mask as an etching mask to form third and fourth patterns, respectively; and
etching upper portions of the substrate using the third and fourth patterns as an etching mask to form first and second active patterns in the cell region and the peripheral circuit region, respectively.

2. The method of claim 1 , further comprising, prior to forming the first and second masks, forming an intermediate layer covering the first and second patterns,
wherein the first and second masks are formed on the intermediate layer.

3. The method of claim 2 , wherein forming the plurality of third masks between the first masks includes:
forming a spacer layer on the intermediate layer to cover the first masks;
forming a third mask layer on the intermediate layer; and
planarizing an upper portion of the third mask layer to form the plurality of third masks.

4. The method of claim 3 , wherein the spacer layer is formed to cover the second mask,
and the method further comprises, after forming the third mask layer:
forming a fourth mask on the third mask layer on a portion of the cell region; and
etching the third mask layer using the fourth mask as an etching mask to remove a portion of the third mask layer on the peripheral circuit region of the substrate.

5. The method of claim 4 , wherein etching the third mask layer using the fourth mask as an etching mask includes forming a third mask layer pattern partially covering the cell region,
and wherein the third masks are formed by planarizing an upper portion of the third mask layer pattern.

6. The method of claim 4 , wherein the fourth mask has a rectangular shape in a plan view.

7. The method of claim 6 , wherein the fourth mask overlaps a central portion of each of the first masks, and ends of each of the first masks extend beyond the fourth mask in the fourth direction.

8. The method of claim 7 , wherein a length of each of the third masks in the fourth direction is less than a length of each of the first masks in the fourth direction.

9. The method of claim 4 , further comprising, prior to forming the fourth mask on the third mask layer:
forming a protection layer on the third mask layer; and
etching the protection layer using the fourth mask as an etching mask to form a protection pattern exposing a portion of the third mask layer on the peripheral circuit region of the substrate.

10. The method of claim 1 , wherein the first and third masks are spaced apart from each other in the first direction by a constant distance.

11. The method of claim 1 , wherein forming the first and second patterns in the cell region and the peripheral circuit region, respectively, of the substrate includes:
forming a layer structure on the substrate; and
forming a plurality of openings in the first direction through the layer structure in the cell region to expose top surfaces of the substrate, respectively, each of the openings extending in the third direction.

12. The method of claim 1 , wherein the first, third and fourth directions have acute angles with one another.

13. The method of claim 1 , wherein the second mask extends in a second direction substantially perpendicular to the first direction.

14. The method of claim 1 , wherein a whole contour of the first patterns is a first rectangular shape, and wherein a whole contour of the first active patterns is a second rectangular shape smaller than and within the first rectangular shape in a plan view, and a portion of the contour of the first active patterns protrudes from the second rectangular shape.

15. A method of forming active patterns, the method comprising:
forming a plurality of first patterns in a first direction on a cell region of a substrate and a second pattern on a peripheral circuit region of the substrate, each of the first patterns extending in a third direction crossing the first direction;
forming a plurality of first masks in the first direction on the first patterns and a second mask on the second pattern, each of the first masks extending in a fourth direction crossing the third direction;
etching the first patterns using the first masks as an etching mask and the second pattern using the second mask as an etching mask to form third and fourth patterns, respectively; and
etching upper portions of the substrate using the third and fourth patterns as an etching mask to form first and second active patterns in the cell region and the peripheral circuit region, respectively, the first active patterns being spaced apart from each other by a constant distance in the third direction and defining a first active pattern columns and the first active pattern columns being spaced apart from each other by a constant distance in the first direction.

16. The method of claim 15 , wherein forming the plurality of first masks further comprises forming a plurality of third masks between the first masks, each of the third masks extending in the fourth direction and wherein etching the first patterns comprises using the first and third masks as an etching mask.

17. The method of claim 16 , wherein the first and third masks are spaced apart from each other in the first direction by a constant distance.

18. The method of claim 15 , wherein the first, third and fourth directions have acute angles with one another.

19. The method of claim 15 , wherein the second mask extends in a second direction substantially perpendicular to the first direction.

20. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of first patterns in a first direction on a cell region of a substrate and a second pattern on a peripheral circuit region of the substrate, each of the first patterns extending in a third direction crossing the first direction;
forming a plurality of first masks in the first direction on the first patterns and a second mask on the second pattern, each of the first masks extending in a fourth direction crossing the third direction;
forming a plurality of third masks between the first masks, each of the third masks extending in the fourth direction;
etching the first patterns using the first and third masks as an etching mask and the second patterns using the second mask as an etching mask to form third and fourth patterns, respectively;
etching upper portions of the substrate using the third and fourth patterns as an etching mask to form first and second active patterns in the cell region and the peripheral circuit region, respectively;
forming a first gate structure through the first active patterns;
forming first and second impurity regions at upper portions of the first active patterns adjacent the first gate structure;
forming a bit line electrically connected to the first impurity region; and
forming a capacitor el

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Tae-Jin
• Yoon Chan-Sic
• Lee Ki-Seok
• Jung Hyeon-Ok
• Kim Dae-Ik
• Kim Bong-Soo
• Kim Yong-Kwan
• Kim Eun-Jung
• Jang Se-Myeong
• Choi Min-Su
• Han Sung-Hee
• Hwang Yoo-Sang

Classifications

• H01L27/10894 Primary

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L21/3086

  Electricity · mapped topic

• H01L27/10852

  Electricity · mapped topic