Protocol level control for system on a chip (SoC) agent reset and power management

Patent metadata

Field	Value
Publication number	US-11914440-B2
Application number	US-202217656378-A
Country	US
Kind code	B2
Filing date	Mar 24, 2022
Priority date	Mar 30, 2018
Publication date	Feb 27, 2024
Grant date	Feb 27, 2024

Abstract

A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

First claim

What is claimed is:

1. A System on a Chip (SoC), comprising:
an interconnect for handling transactional traffic between a plurality of circuit subsystems on the SoC, the interconnect comprising a port, the plurality of circuit subsystems including a first circuit subsystem configured to initiate a subsystem wake-up sequence to enable the first circuit subsystem to resume normal operation, the subsystem wake-up sequence involving:
the first circuit subsystem sending a wake-up request signal over a link to the interconnect in response to a wake-up trigger event while the first circuit subsystem is in an inoperable state and the link is in a quiescent state, the wake-up trigger event comprising an event related to the first circuit subsystem;
the interconnect, in response to detecting the wake-up request signal from the first circuit subsystem, notifying a system controller, the system controller in an awake state, that the wake-up request signal was detected; and

the system controller, in response to the notifying, sending a command over the interconnect to the first circuit subsystem, the command directing the first circuit subsystem to initiate the subsystem wake-up sequence to exit the inoperable state.

2. The SoC of claim 1 , further comprising:
a quiescent manager arranged to place the link in the quiescent state by:
instructing the first circuit subsystem to stop generating transactions;
waiting for outstanding transactions to complete and placing the link in the quiescent state responsive to determining that transactions generated by the first circuit subsystem are complete; and
causing the first circuit subsystem to initiate a sequence to enter the inoperable state.

3. The SoC of claim 1 , further comprising:
a power manager arranged to place the first circuit subsystem into the inoperable state by performing at least one of:
shutting off a clock associated with the first circuit subsystem; or
reducing a power supply to the first circuit subsystem.

4. The SoC of claim 1 , wherein the inoperable state comprises a lower power state in which the first circuit subsystem is provided a lower voltage than a standard operating voltage of the first circuit subsystem.

5. The SoC of claim 1 , wherein the inoperable state comprises an off state in which the first circuit subsystem is provided no voltage or a clock of the first circuit subsystem is disabled.

6. The SoC of claim 1 , wherein the interconnect is configured to act as a proxy on behalf of the first circuit subsystem when the first circuit subsystem is in the inoperable state, the interconnect acting as the proxy after the interconnect drains transactions that the first circuit subsystem has already issued by one or more of:
preventing new transactions from being initiated; or
waiting for outstanding transactions to complete.

7. The SoC of claim 6 , wherein the interconnect is configured to act as a proxy of behalf of the first circuit subsystem until the subsystem wake-up sequence has concluded and the first circuit subsystem has resumed normal operation.

8. The SoC of claim 1 , wherein the wake-up trigger event includes one or more of the following:
a reception, by the first circuit subsystem, of a communication from a source external to the SoC;
a determination, by the first circuit subsystem, of an expiration of a predetermined time period;
a reception, by the first circuit subsystem, of an instruction from the system controller; or
a reception, by the first circuit subsystem, of a valid transaction targeting the first circuit subsystem in the inoperable state.

9. A System on a Chip (SoC), comprising:
an interconnect for handling transactional traffic between a plurality of shared resources on the SoC, the plurality of shared resources directly connected to the interconnect at one or more ports; and
a link connecting a shared resource of the plurality of shared resources to the interconnect, the shared resource configured to initiate a subsystem wake-up sequence when in an inoperable state in response to a wake-up trigger event, the subsystem wake-up sequence arranged to enable the shared resource to resume normal operation and involves:
the shared resource sending a wake-up request signal over the link to the interconnect in response to the wake-up trigger event, while the shared resource is in the inoperable state and the link is in a quiescent state, the wake-up trigger comprising an event related to the shared resource;
the interconnect, in response to detecting the wake-up request signal from the shared resource, notifying a system controller, the system controller in an awake state, that the wake-up request signal was detected; and
the system controller, in response to the notifying, sending a command over the interconnect to the shared resource, the command directing the shared resource to initiate the subsystem wake-up sequence to exit the inoperable state.

10. The SoC of claim 9 , further comprising:
a quiescent manager arranged to place the link in the quiescent state by:
instructing the shared resource to stop generating transactions;
waiting for outstanding transactions to complete and placing the link in the quiescent state responsive to determining that transactions generated by the shared resource are complete; and
causing the shared resource to initiate a sequence to enter the inoperable state.

11. The SoC of claim 9 , further comprising:
a power manager arranged to place the shared resource into the inoperable state by performing at least one of:
shutting off a clock associated with the shared resource; or
reducing a power supply to the shared resource.

12. The SoC of claim 9 , wherein the inoperable state comprises a lower power state in which the shared resource is provided a lower voltage than a standard operating voltage of the shared resource.

13. The SoC of claim 9 , wherein the inoperable state comprises an off state in which the shared resource is provided no voltage or a clock of the shared resource is disabled.

14. The SoC of claim 9 , wherein the interconnect is configured to act as a proxy on behalf of the shared resource when the shared resource is in the inoperable state, the interconnect acting as the proxy after the interconnect drains transactions that the shared resource has already issued by one or more of:
preventing new transactions from being initiated; or
waiting for outstanding transactions to complete.

15. The SoC of claim 14 , wherein the interconnect is configured to act as a proxy of behalf of the shared resource until the subsystem wake-up sequence has concluded and the shared resource has resumed normal operation.

16. The SoC of claim 9 , wherein the wake-up trigger event includes one or more of the following:
a reception, by the shared resource, of a communication from a source external to the SoC;
a determination, by the shared resource, of an expiration of a predetermined time period;
a reception, by the shared resource, of an instruction from the system controller; or
a reception, by the shared resource, of a valid transaction targeting the shared resource in the inoperable state.

17. A method comprising:
determining, by a circuit subsystem that is in an inoperable state, that a wake-up trigger event has occurred, the wake-up trigger event comprising an event related to the circuit subsystem;
responsive to determining that the wake-up trigger event has occurred, transmitting, by the circuit subsystem, over a link that is in a quiescent state, and to an interconnect that couples the circuit subsystem to one or mo

Assignees

• Google Llc

Inventors

• Desai Shailendra
• Pearce Mark
• Jain Amit
• Patel Jaymin

Classifications

• Y02D30/00

  Reducing energy consumption in communication networks · CPC title

• G06F1/24 Primary

  Resetting means · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F9/542

  Event management; Broadcasting; Multicasting; Notifications · CPC title