HW-controlled power domains with automatic power-on request

Patent metadata

Field	Value
Publication number	US-9727114-B2
Application number	US-201414496553-A
Country	US
Kind code	B2
Filing date	Sep 25, 2014
Priority date	Sep 25, 2014
Publication date	Aug 8, 2017
Grant date	Aug 8, 2017

Abstract

Systems and methods related to hardware controlled power domains in a hardware system (e.g., an integrated circuit) are disclosed. In one embodiment, fully automatic power on and power off of the power domains in the hardware system is provided without software involvement. In this manner, power up and power down times for the power domains are substantially reduced or minimized, which in turn enables shorter active times for the power domains and thus reduced power consumption (e.g., reduced leakage when hardware in the power domains is idle).

First claim

What is claimed is:

1. A hardware system comprising:
a hardware block comprising one or more hardware components;
a hardware power controller configured to control one or more power domains of the hardware system, the one or more power domains comprising a power domain of the hardware block; and
a hardware interface configured to:
receive at least one message for the hardware block;
store the at least one message;
in response to receiving the at least one message for the hardware block, activate a power request from the hardware interface to the hardware power controller to thereby request that the power domain of the hardware block be powered up, wherein the hardware power controller is configured to power up the power domain of the hardware block in response to activation of the power request from the hardware interface and the hardware block is configured to, in response to the power domain of the hardware block being powered up, activate a power request from the hardware block to the hardware power controller to thereby request that power to the hardware block be maintained until the power request from the hardware block is de-activated;
receive an indication from the hardware block that the hardware block is ready to accept messages from the hardware interface; and
provide the at least one message to the hardware block in response to receiving the indication from the hardware block that the hardware block is ready to accept messages from the hardware interface.

2. The hardware system of claim 1 wherein the hardware interface is further configured to de-activate the power request from the hardware interface to the hardware power controller upon determining that there are no more messages received by the hardware interface for the hardware block that are to be provided to the hardware block.

3. The hardware system of claim 1 wherein:
the hardware block is further configured to de-activate the power request from the hardware block to the hardware power controller upon determining that there are no more messages received from the hardware interface to be processed by the hardware block; and
the hardware power controller is further configured to power down the power domain of the hardware block in response to de-activation of the power request from the hardware interface and de-activation of the power request from the hardware block.

4. The hardware system of claim 3 wherein the hardware power controller is further configured to indicate, to the hardware block, that the power domain of the hardware block is being powered down to thereby indicate to the hardware block that the hardware block is not to accept messages from the hardware interface.

5. The hardware system of claim 1 wherein, in response to activation of the power request from the hardware interface, the hardware power controller is further configured to:
wait for power to the power domain of the hardware block to be stable; and
when the power to the power domain of the hardware block is stable, then activate the hardware block.

6. The hardware system of claim 5 wherein, in order to activate the hardware block, the hardware power controller is configured to:
de-activate one or more isolation cells that operate to isolate the power domain when power to the power domain is de-activated;
de-activate a reset of the hardware block; and
activate a system on request for the hardware block to thereby inform the hardware block that power to the hardware block is activated.

7. The hardware system of claim 5 wherein, in response to being activated, the hardware block is further configured to:
activate a message accept from the hardware block to the hardware interface to thereby indicate that the hardware block is ready to accept messages from the hardware interface; and
activate a system acknowledgement from the hardware block to the hardware power controller.

8. The hardware system of claim 7 wherein:
the hardware interface is further configured to de-activate the power request from the hardware interface to the hardware power controller when there are no more messages received by the hardware interface for the hardware block that are to be provided to the hardware block;
the hardware block is further configured to de-activate the power request from the hardware block to the hardware power controller when there are no more messages received by the hardware block from the hardware interface that are to be processed by the hardware block; and
the hardware power controller is further configured to power down the power domain of the hardware block in response to de-activation of the power request from the hardware interface and de-activation of the power request from the hardware block.

9. The hardware system of claim 8 wherein:
in order to power down the power domain of the hardware block, the hardware power controller is further configured to inform the hardware block that power to the hardware block is being de-activated; and
in response to being informed that the power to the hardware block is being de-activated, the hardware block is further configured to de-activate the message accept from the hardware block to the hardware interface to thereby indicate that the hardware block is no longer accepting messages from the hardware interface.

10. The hardware system of claim 9 wherein:
after de-activating the message accept from the hardware block to the hardware interface, the hardware block is further configured to determine whether any messages were received from the hardware interface while de-activating the message accept from the hardware block to the hardware interface; and
if no messages were received from the hardware interface while de-activating the message accept from the hardware block to the hardware interface, the hardware block is configured to continue with power down of the power domain of the hardware block; and
if one or more messages were received from the hardware interface while deactivating the message accept from the hardware block to the hardware interface, the hardware block is configured to terminate power down of the power domain of the hardware block.

11. The hardware system of claim 10 wherein:
in order to continue power down, the hardware block is further configured to de-activate the system acknowledgement from the hardware block to the hardware power controller; and
in response to the de-activation of the system acknowledgement, the hardware power controller is further configured to de-activate the power to the power domain.

12. The hardware system of claim 10 wherein:
in order to terminate power down, the hardware block is further configured to activate the power request from the hardware block to the hardware power controller, de-activate the system acknowledgement from the hardware block to the hardware power controller, and activate the message accept from the hardware block to the hardware interface;
in response to de-activation of the system acknowledgement, the hardware power controller is further configured to inform the hardware block that power to the hardware block is being activated; and
in response to being informed that power to the hardware block is being activated, the hardware block is further configured to activate the system acknowledgement from the hardware block to the hardware power controller.

13. The hardware system of claim 1 wherein the power domain comprises the hardware block and at least one additional hardware block, and the hardware system further comprises:
circuitry configured to combine the power request from the hardware interface for the hardware block and at least one additional power req

Assignees

• Ericsson Telefon Ab L M

Inventors

• Malmberg Magnus
• Arvidsson Alberth

Classifications

• G06F30/30

  Circuit design · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F21/81

  by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations · CPC title

• H04L12/10

  Current supply arrangements · CPC title

• G06F1/3287 Primary

  by switching off individual functional units in the computer system · CPC title