Hardware apparatuses and methods to perform transactional power management

Patent metadata

Field	Value
Publication number	US-9733689-B2
Application number	US-201514752896-A
Country	US
Kind code	B2
Filing date	Jun 27, 2015
Priority date	Jun 27, 2015
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

First claim

What is claimed is:

1. A hardware apparatus comprising:
a hardware processor having a core;
a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain;
a power transaction unit to:
assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution,
perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and
perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction; and

a memory transaction unit to perform a commit of a first thread and a second thread after concurrent execution of the first thread on the core and the second thread on a second core of the hardware processor unless the first thread and the second thread are to modify a same memory address.

2. The hardware apparatus of claim 1 , wherein the first power transaction and the second power transaction each include multiple instructions.

3. The hardware apparatus of claim 1 , further comprising a plurality of power state registers to receive the power management command for each domain.

4. The hardware apparatus of claim 3 , wherein the conflict is the first power transaction to write to a power state register that the second power transaction has written.

5. The hardware apparatus of claim 1 , wherein the power transaction unit is to not issue a lock.

6. The hardware apparatus of claim 1 , wherein the conflict is the first power transaction and the second power transaction to write conflicting power management commands for a shared power domain.

7. The hardware apparatus of claim 1 , wherein, when there is the conflict, a transition of a power domain in response to execution of the second power transaction is only visible to other transactions after the commit of the second power transaction.

8. The hardware apparatus of claim 1 , wherein the power transaction unit is to perform an abort of the second power transaction when there is the conflict between the first power transaction and the second power transaction instead of the commit of the second power transaction.

9. A method comprising:
providing a plurality of power domains of a hardware apparatus including a hardware processor to transition to one of a plurality of power states in response to a power management command for each power domain;
assigning a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution;
performing a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction;
performing an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction; and
performing a commit of a first thread and a second thread after concurrent execution of the first thread and the second thread on the hardware processor unless the first thread and the second thread are to modify a same memory address.

10. The method of claim 9 , wherein the first power transaction and the second power transaction each include multiple instructions.

11. The method of claim 9 , further comprising receiving the power management command for each domain at a power state register.

12. The method of claim 11 , wherein the conflict is the first power transaction writing to a power state register that the second power transaction has written.

13. The method of claim 9 , wherein no lock is issued.

14. The method of claim 9 , wherein the conflict is the first power transaction and the second power transaction writing conflicting power management commands for a shared power domain.

15. The method of claim 9 , wherein, when there is the conflict, a transition of a power domain in response to execution of the second power transaction is only visible to other transactions after the commit of the second power transaction is performed.

16. The method of claim 9 , further comprising performing an abort of the second power transaction when there is the conflict between the first power transaction and the second power transaction instead of the commit of the second power transaction.

17. A non-transitory machine readable storage medium having stored program code that when processed by a machine causes a method to be performed, the method comprising:
providing a plurality of power domains of a hardware apparatus including a hardware processor to transition to one of a plurality of power states in response to a power management command for each power domain;
assigning a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution;
performing a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction;
performing an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction; and
performing a commit of a first thread and a second thread after concurrent execution of the first thread and the second thread on the hardware processor unless the first thread and the second thread are to modify a same memory address.

18. The non-transitory machine readable storage medium of claim 17 , wherein the first power transaction and the second power transaction each include multiple instructions.

19. The non-transitory machine readable storage medium of claim 17 , wherein the method further comprises receiving the power management command for each domain at a power state register.

20. The non-transitory machine readable storage medium of claim 19 , wherein the conflict is the first power transaction writing to a power state register that the second power transaction has written.

21. The non-transitory machine readable storage medium of claim 17 , wherein the method includes no lock being issued.

22. The non-transitory machine readable storage medium of claim 17 , wherein the conflict is the first power transaction and the second power transaction writing conflicting power management commands for a shared power domain.

23. The non-transitory machine readable storage medium of claim 17 , wherein, when there is the conflict, a transition of a power domain in response to execution of the second power transaction is only visible to other transactions after the commit of the second power transaction is performed.

24. The non-transitory machine readable storage medium of claim 17 , wherein the method further comprises performing an abort of the second power transaction when there is the conflict between the first power transaction and the second power transaction instead of the commit of the second power transaction.

Assignees

• Intel Corp

Inventors

• Muralidhar Rajeev D
• Seshadri Harinarayanan
• Krishnakumar Nivedha
• Singh Youvedeep
• Partiwala Suketu R

Classifications

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/00 Primary

  Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 (architectures of general purpose stored program computers G06F15/76) · CPC title

• G06F9/52

  Program synchronisation; Mutual exclusion, e.g. by means of semaphores · CPC title

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title