Single cycle arbitration within an interconnect

Patent metadata

Field	Value
Publication number	US-9514074-B2
Application number	US-201313940915-A
Country	US
Kind code	B2
Filing date	Jul 12, 2013
Priority date	Feb 13, 2009
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An interconnect within an integrated circuit provides arbitration to select one of a plurality of signal inputs for connection to a signal output. The arbitration applied uses a first arbitration parameter value, in the form of a time stamp value, and, if two or more signal inputs share such a time stamp value, then uses a second arbitration parameter, in the form of a least recently granted value. The time increment applied to the time stamp value associated with each signal input when it is granted access to the signal output is selected to reflect the quality of service to be associated with that signal input. When a comparison is made between time stamp values, the lowest time stamp value is given priority. A large time increment value corresponds to a low priority (quality of service).

First claim

We claim:

1. Interconnect circuitry for providing a communication path for data between a selected one of N signal inputs and a signal output, where N is an integer of two or more, said interconnect circuitry comprising:
multiplexing circuitry configured to select one of said N signal inputs as a selected signal input in dependence upon a selection signal and to connect said selected signal input to said signal output to send given data; and
arbitration circuitry configured to generate said selection signal so as to perform an arbitration in a single cycle between a plurality of said N signal inputs having respective data to send, wherein
said arbitration is performed in dependence upon:
(i) respective values of a first arbitration parameter associated with each of said plurality of said N signal inputs; and
(ii) when two or more of said plurality of said N signal inputs have a common value of said first arbitration parameter, a second arbitration parameter associated with each of said two or more of plurality of said N signal inputs, said second arbitration parameter having a different value for each of said two or more of said plurality of said N signal inputs.

2. Interconnect circuitry as claimed in claim 1 , wherein said N signal inputs are coupled to respective data source circuits and said signal output is coupled to a data destination circuit, said interconnect circuitry, said data source circuits and said data destination circuit all formed on a single integrated circuit.

3. Interconnect circuitry as claimed in claim 1 , comprising M signal outputs, where M is an integer of one or more.

4. Interconnect circuitry as claimed in claim 1 , wherein first arbitration parameter has a value representing a quality of service level associated with data sent from a corresponding signal input.

5. Interconnect circuitry as claimed in claim 1 , wherein said second arbitration parameter is allocated to each of said N signal inputs to represent a relative order in which said N signal inputs were previously selected as said selected signal input.

6. Interconnect circuitry as claimed in claim 1 , wherein said first arbitration parameter and said second arbitration parameter are concatenated to form a combined arbitration parameter with said second arbitration parameter controlling a least significant bit portion of said combined arbitration parameter.

7. Interconnect circuitry as claimed in claim 3 , wherein M=N.

8. Interconnect circuitry as claimed in claim 4 , wherein said first arbitration parameter is a time stamp value and said time stamp value for said selected signal input is updated when said selected signal input sends data.

9. Interconnect circuitry as claimed in claim 6 , wherein said arbitration circuitry comprises thermometer coding circuitry configured to thermometer code said combined arbitration parameter of each of said N signal inputs to generate respective thermometer coded arbitration parameters.

10. Interconnect circuitry as claimed in claim 8 , wherein said time stamp value for said selected input is updated by adding a time increment value to said time stamp value for said selected input, said time increment value varying in dependence upon a quality of service level associated with said selected signal input.

11. Interconnect circuitry as claimed in claim 9 , wherein said arbitration circuitry comprises comparison circuitry configured to compare said thermometer coded arbitration parameters to identify which of said N signal inputs is selected as said selected signal input.

12. Interconnect circuitry as claimed in claim 10 , wherein said arbitration circuitry is configured to compare time stamp values of a plurality of signal inputs having data to send and to eliminate from selection as said selected signal input any of said plurality of inputs having data to send that have a higher time stamp value that one or more other of said plurality of signal inputs having data to send.

13. Interconnect circuitry as claimed in claim 11 , wherein said comparison circuitry comprises a plurality of signal lines each precharged to predetermined signal level and selectively discharged in dependence upon said thermometer coded arbitration parameters.

14. Interconnect circuitry as claimed in claim 12 , wherein as said time increment value associated with a given signal input increases, a relative priority for access to said signal output by said given signal input among said N signal inputs decreases.

15. Interconnect circuitry as claimed in claim 13 , wherein said plurality of signal lines is divided into 2 X groups of signal lines each associated with a different value of said first arbitration parameter, where X is the bit length of said first arbitration parameter, said comparison circuitry configured to discharge all signal lines within a given group of signal lines if any of N signal inputs has a first arbitration parameter indicative of a higher priority than a first arbitration parameter of said given group.

16. Interconnect circuitry as claimed in claim 8 , wherein said arbitration circuitry is configured such that when at least one of said time stamp values associated with said N signal inputs reaches a threshold level, then all of said time stamp values are divided by two.

17. Interconnect circuitry as claimed in claim 13 , wherein said signal lines are also used to communicate said data.

18. Interconnect circuitry as claimed in claim 15 , wherein each group of signal lines contains N signal lines with different signal lines within each group of signal lines corresponding to different values of said second arbitration parameter, said comparison circuitry configured to discharge said different signal lines within a threshold group associated with a highest priority first arbitration parameter in dependence upon respective unique values of said second arbitration parameter associated with said N signal inputs such that a single signal line within said threshold group remains charged thereby identifying which of said N signal inputs is to be selected as said selected signal input.

19. Interconnect circuitry for providing a communication path for data between a selected one of N signal inputs and a signal output, where N is an integer of two or more, said interconnect circuitry comprising:
multiplexing means for selecting one of said N signal inputs as a selected signal input in dependence upon a selection signal and to connect said selected signal input to said signal output to send given data; and
arbitration means for generating said selection signal so as to perform an arbitration in a single cycle between a plurality of said N signal inputs having respective data to send, wherein
said arbitration is performed in dependence upon:
(i) respective values of a first arbitration parameter associated with each of said plurality of said N signal inputs; and
(ii) when two or more of said plurality of said N signal inputs have a common value of said first arbitration parameter, a second arbitration parameter associated with each of said two or more of plurality of said N signal inputs, said second arbitration parameter having a different value for each of said two or more of said plurality of said N signal inputs.

20. A method of providing a communication path for data between a selected one of N signal inputs and a signal output, where N is an integer of two or more, said method comprising the steps of:
selecting one of said N signal inputs as a selected signal input in dependence upon a selection signal and to connect sa

Assignees

• Univ Michigan Regents

Inventors

• Jeloka Supreet
• Abeyratne Sandunmalee Nilmini
• Dreslinski Ronald George
• Das Reetuparna
• Mudge Trevor Nigel
• Blaauw David Theodore

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/374 Primary

  using a self-select method with individual priority code comparator · CPC title

• G06F13/1642

  with request queuing · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title