Handling a partition reset in a multi-root system

Patent metadata

Field	Value
Publication number	US-2016357696-A1
Application number	US-201514865005-A
Country	US
Kind code	A1
Filing date	Sep 25, 2015
Priority date	Jun 4, 2015
Publication date	Dec 8, 2016
Grant date	—

Abstract

In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus comprising:
a semiconductor die including but not limited to:
a plurality of agents, at least a first subset of the plurality of agents associated with a first root space value to define a first root space and at least a second subset of the plurality of agents associated with a second root space value to define a second root space, wherein a first agent of the plurality of agents is associated with the first root space and the second root space; and
a fabric coupled to the plurality of agents via a fabric primary interface, the fabric primary interface including at least one master interface to initiate transactions and at least one target interface to receive transactions.

2 . The apparatus of claim 1 , wherein the first agent is to receive a reset prepare signal to inform the first agent that the first root space is to be reset, and responsive thereto, send an acknowledgement signal to acknowledge the reset prepare signal.

3 . The apparatus of claim 2 , wherein the first agent is to receive one or more transactions for the first root space and terminate the one or more transactions responsive to the reset prepare signal, wherein the first root space is in a reset state when the one or more transactions are received.

4 . The apparatus of claim 3 , wherein the first agent is to receive a boot prepare signal to inform the first agent that the reset of the first root space has completed, and responsive thereto, send a boot prepare acknowledge signal.

5 . The apparatus of claim 4 , wherein the first agent is to receive and handle one or more additional transactions for first root space received in the first agent after receipt of the boot prepare signal.

6 . The apparatus of claim 3 , wherein the first agent, while the first root space is in the reset state, is to drop a posted transaction and a completion transaction, and send an unsupported request completion for a non-posted transaction.

7 . The apparatus of claim 3 , wherein the first agent is to receive and handle at least one transaction for the second root space received in the first agent while the first root space is in the reset state.

8 . The apparatus of claim 2 , further comprising a router having a sideband message interface to couple to the first agent via a sideband interconnect, and wherein the first agent is to receive the reset prepare signal via the sideband interconnect from a power controller of a system on a chip (SoC) comprising the semiconductor die.

9 . The apparatus of claim 1 , wherein a second agent of the second subset of the plurality of agents, responsive to a power gate signal from a power controller to indicate that the second root space is to be reset, is to send a signal to the fabric to inform the fabric that the second agent is to be power gated, wherein the fabric is to terminate one or more transactions directed to the second agent, responsive to receipt of the signal from the second agent.

10 . The apparatus of claim 1 , wherein the fabric is to enable independent reset of the plurality of root spaces.

11 . A computer readable storage medium including information that, when manufactured into a system on a chip (SoC), is to configure the SoC to:
receive, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; send, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receive one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminate the one or more transactions responsive to the reset prepare signal, wherein the first root space is in a reset state when the one or more transactions are received.

12 . The computer readable medium of claim 11 , wherein the information, when manufactured into the SoC, is to configure the SoC to:
receive, via the sideband interface, a boot prepare signal, the boot prepare signal to inform the multi-root agent that the reset has completed; send a boot prepare acknowledgement signal; and handle one or more additional transactions via first root space received in the multi-root agent after receipt of the boot prepare signal.

13 . The computer readable medium of claim 11 , wherein the information, when manufactured into the SoC, is to configure the SoC to drop a posted transaction and a completion transaction to terminate the posted transaction and the completion transaction.

14 . The computer readable medium of claim 11 , wherein the information, when manufactured into the SoC, is to configure the SoC to send an unsupported request completion for a non-posted transaction to terminate the non-posted transaction.

15 . The computer readable medium of claim 11 , wherein the information, when manufactured into the SoC, is to configure the SoC to receive and handle at least one transaction for the second root space while the first root space is in the reset state.

16 . The computer readable medium of claim 11 , wherein the information, when manufactured into the SoC, is to configure the SoC to receive the reset prepare signal from a power controller of the SoC.

17 . A system-on-chip (SoC) comprising:
at least one core to execute instructions; a coherent interconnect coupled to the at least one core; a plurality of agents, including a first agent associated with a first root space value, a second agent associated with a second root space value, and a third agent associated with the first root space value and the second root space value, the first root space value to define a first root space and the second root space value to define a second root space; a fabric coupled to the coherent interconnect and to at least some of the plurality of agents; and a router coupled to at least some of the plurality of agents via a sideband interconnect.

18 . The SoC of claim 17 , wherein the first agent is to receive one or more transactions for the first root space from the fabric and terminate the one or more transactions when the first root space is in a reset state, and after receipt of a boot prepare signal to inform the first agent that a reset of the first root space has completed, to receive and handle one or more additional transactions for first root space.

19 . The SoC of claim 17 , further comprising at least one component coupled to the fabric via a bridge, wherein the at least one component is of an open core protocol (OCP) or an ARM advanced microcontroller bus architecture (AMBA) protocol.

20 . The SoC of claim 17 , wherein the at least one core comprises a first in-order core and a first out-of-order core.

Assignees

• Intel Corp

Inventors

• Klinglesmith Michael T
• Hunsaker Mikal C
• Knolla William
• Singh Hartej

Classifications

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title