Protocol level control for system on a chip (SoC) agent reset and power management
US-11914440-B2 · Feb 27, 2024 · US
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Pearce Mark patents
Pearce Mark is listed as an inventor on 6 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Pearce Mark |
| Total patents | 6 |
| First publication | Sep 23, 2021 |
| Latest publication | Feb 27, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Procedures for improving efficiency of an interconnect fabric on a system on chip
US-11640362-B2 · May 2, 2023 · US
Protocol Level Control for System on a Chip (SOC) Agent Reset and Power Management
US-2022291730-A1 · Sep 15, 2022 · US
Protocol Level Control for System on a Chip (soc) Agent Reset and Power Management
US-2022214731-A1 · Jul 7, 2022 · US
Protocol level control for system on a chip (SOC) agent reset and power management
US-11340671-B2 · May 24, 2022 · US
Procedures for improving efficiency of an interconnect fabric on a system on chip
US-2021294762-A1 · Sep 23, 2021 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Google Llc | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/542 | 6 |
| G06F15/7807 | 6 |
| Y02D30/00 | 4 |
| G06F1/3243 | 4 |
| G06F11/1402 | 4 |