Semiconductor package

Patent metadata

Field	Value
Publication number	US-11901301-B2
Application number	US-202117306555-A
Country	US
Kind code	B2
Filing date	May 3, 2021
Priority date	Jun 25, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A semiconductor package includes a frame structure having a core portion and a lower pad under the core portion. A cavity penetrates the core portion, and a semiconductor chip is arranged in the cavity and has an active surface on which a bump pad is arranged and a non-active surface facing the active surface. A redistribution structure is positioned under the frame structure and the semiconductor chip, and is connected to the lower pad and the bump pad. A molding member covers the frame structure and the semiconductor chip and fills the cavity. The molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pad, and the bump pad.

First claim

What is claimed is:

1. A semiconductor package comprising:
a frame structure comprising a core portion and a plurality of lower pads under the core portion, wherein a cavity penetrates the core portion;
a semiconductor chip arranged in the cavity, wherein the semiconductor chip comprises an active surface on which a plurality of bump pads are arranged and a non-active surface opposite the active surface, wherein the bump pads protrude from the active surface of the semiconductor chip and have a polygonal column shape or a cylindrical shape;
a redistribution structure under the frame structure and the semiconductor chip, wherein the redistribution structure is connected to the lower pads and the bump pads; and
a molding member that is on the frame structure and the semiconductor chip, and that is in the cavity,
wherein the molding member surrounds a lower surface of the frame structure, the active surface of the semiconductor chip, the lower pads, and the bump pads, wherein the molding member contacts a side surface of the bump pads, wherein the molding member covers an upper surface of the core portion, a lower surface of the core portion, and a side surface of the core portion, and wherein the molding member fills a space between the lower pads and a space between the bump pads, and wherein the molding member contacts an upper surface of the redistribution structure.

2. The semiconductor package of claim 1 , wherein the semiconductor chip includes a side surface that connects the active surface to the non-active surface, and
wherein the molding member surrounds the active surface, the non-active surface, and the side surface of the semiconductor chip.

3. The semiconductor package of claim 1 , wherein the lower pads protrude from the core portion, and
wherein a lower surface of the lower pads, a lower surface of the bump pads, and a lower surface of the molding member are coplanar.

4. The semiconductor package of claim 3 , wherein a lower surface of the core portion and the active surface are spaced apart from the redistribution structure.

5. The semiconductor package of claim 3 , wherein the lower surface of the bump pads is a flat surface.

6. The semiconductor package of claim 5 , wherein a surface roughness of a lower surface of the lower pads is substantially equal to a surface roughness of the lower surface of the bump pads.

7. The semiconductor package of claim 1 , wherein the frame structure further comprises:
a plurality of upper pads on the core portion; and
a plurality of through vias that connect the upper pads to the lower pads, wherein the through vias have an hourglass shape with a concave middle portion.

8. The semiconductor package of claim 1 , wherein the bump pads have a thickness of about 5 μm to about 20 μm from the active surface to an upper surface of the redistribution structure.

9. The semiconductor package of claim 1 , wherein the redistribution structure comprises a redistribution line and a redistribution via connected to the redistribution line,
wherein the redistribution via has a tapered shape that increases in width as a distance from the semiconductor chip increases.

10. A semiconductor package comprising:
a first sub-package comprising a first semiconductor chip;
a second sub-package on the first sub-package and comprising a second semiconductor chip; and
a connection structure connecting the first sub-package to the second sub-package,
wherein the first sub-package comprises:
a frame structure comprising a core portion and a lower pad under the core portion, wherein a cavity penetrates the core portion;
wherein the first semiconductor chip is arranged in the cavity, wherein the first semiconductor chip comprises an active surface on which a bump pad is arranged and a non-active surface opposite the active surface, wherein the bump pad protrudes from the active surface of the semiconductor chip and has a polygonal column shape or a cylindrical shape;
a redistribution structure under the frame structure and the first semiconductor chip, wherein the redistribution structure is connected to the lower pad and the bump pad; and
a molding member that is on the frame structure and the first semiconductor chip, and that is in the cavity, wherein the molding member contacts a side surface of the bump pad, and wherein the molding member covers an upper surface of the core portion, a lower surface of the core portion, and a side surface of the core portion,
wherein the lower pad protrudes from the core portion, and
wherein a lower surface of the lower pad, a lower surface of the bump pad, and a lower surface of the molding member are coplanar.

11. The semiconductor package of claim 10 , wherein the frame structure comprises:
an upper pad on the core portion; and
a through via connecting the upper pad to the lower pad, and
wherein the connection structure is connected to the upper pad.

12. The semiconductor package of claim 10 , wherein the molding member surrounds all surfaces of the semiconductor chip, a lower surface of the frame structure, an upper surface of the redistribution structure, a side surface of the lower pad, and a side surface of the bump pad.

13. The semiconductor package of claim 10 , wherein the lower surface of the lower pad and the lower surface of the bump pad are flat surfaces, and
wherein a surface roughness of the lower surface of the lower pad is substantially equal to as a surface roughness of the lower surface of the bump pad.

14. The semiconductor package of claim 10 , wherein the first semiconductor chip and the second semiconductor chip are of different types.

15. A semiconductor package comprising:
a frame structure comprising a core portion, an upper pad on the core portion, a lower pad under the core portion, and a through via that connects the upper pad to the lower pad, and wherein a cavity penetrates the core portion;
a semiconductor chip arranged in the cavity and having an active surface on which a bump pad is arranged and a non-active surface opposite the active surface, wherein the bump pad protrudes from the active surface of the semiconductor chip and has a polygonal column shape or a cylindrical shape;
a redistribution structure under the frame structure and the semiconductor chip and including a redistribution line and a redistribution via connected to the redistribution line, the redistribution via having a tapered shape that increases in width as a distance from the semiconductor chip increases;
a molding member that is on the frame structure, the semiconductor chip, and the redistribution structure, and that is in the cavity; and
an external connection terminal arranged under the redistribution structure and electrically connected to the redistribution line and the redistribution via,
wherein the molding member surrounds all surfaces of the semiconductor chip, a lower surface of the frame structure, an upper surface of the redistribution structure, a side surface of the lower pad, and contacts a side surface of the bump pad, and wherein the molding member covers an upper surface of the core portion, a lower surface of the core portion, and a side surface of the core portion.

16. The semiconductor package of claim 15 , wherein the lower pad and the bump pad include substantially the same material, and
wherein a surface roughness of a lower surface of the lower pad is substantially the same as a surface roughness of a lower surface of the bump pad.

17. The semiconductor package of claim 16 , wherein an arithmetical average roughness of the surface roughness of the lower

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeongho
• Lee Doohwan

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title