Transistor having wrap-around source/drain contacts and under-contact spacers

Patent metadata

Field	Value
Publication number	US-11876136-B2
Application number	US-202217590193-A
Country	US
Kind code	B2
Filing date	Feb 1, 2022
Priority date	Oct 16, 2019
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

Embodiments of the invention are directed to a semiconductor device structure that includes a first channel region over a substrate, a second channel region over the first channel region, and a merged source or drain (S/D) region over the substrate and adjacent to the first channel region and the second channel region. The merged S/D region is communicatively coupled to the first channel region and the second channel region. A wrap-around S/D contact is configured such that it is on a top surface, sidewalls, and a bottom surface of the merged S/D region.

First claim

What is claimed is:

1. A semiconductor device structure comprising:
a first channel region over a substrate;
a second channel region over the first channel region;
a source or drain (S/D) trench having a S/D trench region and a bottom trench region;
a liner within the bottom trench region;
wherein the liner comprises a first liner element on a bottom surface of the bottom trench region;
wherein the liner further comprises a second liner element on sidewalls of the bottom trench region;
an under-contact spacer on the first liner element and along first portions of the second liner element such that second portions of the second liner element extend above the under-contact spacer;
a merged S/D region within the S/D trench region and adjacent to the first channel region and the second channel region, wherein the merged S/D region comprises a top surface, sidewalls, and a bottom surface; and
a wrap-around S/D contact configured such that a portion of the wrap-around S/D contact is between the bottom surface of the merged S/D region and a bi-layer bottom spacer comprising the liner and the under-contact spacer.

2. The semiconductor device structure of claim 1 , wherein the wrap-around S/D contact is configured to extend completely around a circumference of the merged S/D region.

3. The semiconductor device structure of claim 2 , wherein the circumference of the merged S/D region comprises the top surface, the sidewalls, and the bottom surface of the merged S/D region.

4. The semiconductor device structure of claim 1 , wherein the merged S/D region comprises an epitaxial merged S/D region.

5. The semiconductor device structure of claim 4 , wherein the epitaxial merged S/D region is communicatively coupled to the first channel region.

6. The semiconductor device structure of claim 5 , wherein the epitaxial merged S/D region is communicatively coupled to the second channel region.

7. The semiconductor device structure of claim 1 , wherein the bi-layer bottom spacer is positioned between the wrap-around S/D contact and the substrate.

8. The semiconductor device structure of claim 1 , wherein the liner comprises a nitride material.

9. The semiconductor device structure of claim 1 , wherein the under-contact spacer layer comprises an oxide material.

10. A semiconductor device structure comprising:
a channel region over a substrate;
a source or drain (S/D) trench over the substrate, wherein the S/D trench comprises a bottom trench region extending below a major surface of the substrate;
a liner within the bottom trench region;
wherein the liner comprises a first liner element on a bottom surface of the bottom trench region;
wherein the liner further comprises a second liner element on sidewalls of the bottom trench region;
an under-contact spacer on the first liner and along first portions of the second liner element such that second portions of the second liner element extend above the under-contact spacer;
a S/D region within the S/D trench and adjacent to the channel region, wherein the S/D region comprises a top surface, sidewalls, and a bottom surface, wherein the S/D region does not extend below the major surface of the substrate and does not extend into the bottom trench region;
wherein the S/D region is communicatively coupled to the channel region; and
a wrap-around S/D contact configured such that a portion of the wrap-around S/D contact is beneath the bottom surface of the S/D region.

11. The semiconductor device structure of claim 10 , wherein the wrap-around S/D contact is configured to extend completely around a circumference of the S/D region.

12. The semiconductor device structure of claim 11 , wherein the circumference of the S/D region comprises the top surface, the sidewalls, and the bottom surface of the S/D region.

13. The semiconductor structure method of claim 10 further comprising a bi-layer bottom spacer configured to include the liner and the under-contact spacer.

14. The semiconductor device structure of claim 13 , wherein the bi-layer bottom spacer is positioned between the wrap-around S/D contact and the substrate.

15. The semiconductor device structure of claim 10 , wherein the liner comprises a nitride material.

16. The semiconductor device structure of claim 15 , wherein the under-contact spacer layer comprises an oxide spacer material.

17. The semiconductor device structure of claim 10 , wherein:
the channel region comprises a first channel region and a second channel region;
the S/D region comprises a merged S/D region adjacent to the first channel region and the second channel region; and
the merged S/D region is communicatively coupled to the first channel region and the second channel region.

18. A semiconductor device structure comprising:
a channel region formed over a substrate;
a source or drain (S/D) trench formed over the substrate, wherein the S/D trench comprises a bottom trench region configured to extend into the substrate;
a S/D region formed within the S/D trench and adjacent to the channel region;
wherein the S/D region does not extend below a major surface of the substrate and does not extend into the bottom trench region;
wherein the S/D region is communicatively coupled to the channel region;
a wrap-around S/D contact formed on a top surface, sidewalls, and a bottom surface of the S/D region; and
an under-contact spacer formed within the bottom trench region;
wherein the under-contact spacer is positioned between the wrap-around S/D contact and the substrate;
wherein the under-contact spacer comprises a first under-contact spacer layer and a second under-contact spacer layer;
wherein the first under-contact spacer layer comprises a liner at least partially positioned beneath a bottom surface of the second under-contact spacer layer; and
wherein the second under-contact spacer layer comprises an etched spacer.

19. The semiconductor device structure of claim 18 , wherein:
the channel region comprises a first channel region and a second channel region; and
the liner is further at least partially positioned on a sidewall of the second under-contact spacer layer.

20. The semiconductor device structure of claim 19 , wherein:
the S/D region comprises a merged S/D region adjacent to the first channel region and the second channel region;
the merged S/D region is communicatively coupled to the first channel region and the second channel region; and
the liner is further at least partially positioned higher than a top surface of the second under-contact spacer layer.

Assignees

• IBM
• Int Business Machine Corporation

Inventors

• Song Yi
• Joseph Praveen
• Greene Andrew
• Cheng Kangguo

Classifications

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/0193

  the components including FinFETs · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title